SUMMARYThe body-driven variant of the gain-boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain-boosting technique, the proposed body-driven approach reduces the minimum supply requirement by two thresholds in a rail-to-rail amplifier exploiting two complementary input stage topologies. Simulations using a 130-nm process show that a 0.9-V power supply is adequate for a single-stage rail-to-rail amplifier providing a 56-dB gain, which is 18 dB higher than that achieved by the same architecture but using the traditional cascoding approach. The main drawbacks are that the solution requires a twin-tub process and an additional bias section.
In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology. We demonstrate that it is possible to recover the secret key of a cryptographic core by exploiting this data dependence by means of different statistical distinguishers. For the first time in the literature we formulate the Attack Exploiting Static Power (AESP) as a univariate attack by using the mutual information approach to quantify the information that leaks through the static power side channel independently from the adopted leakage model. This analysis shows that countermeasures conceived to protect cryptographic hardware from attacks based on dynamic power consumption (e.g. WDDL, MDPL, SABL) still exhibit a leakage through the static power side channel. Finally, we show that the Time Enclosed Logic (TEL) concept does not leak information through the static power (even in the worst case scenario in which the attacker can stop the clock signal) and is suitable to be used as a countermeasure against both attacks explointig dynamic power and attacks exploiting static power
Solutions for the design of low-voltage sample-andhold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4-VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and −56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches
A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band
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