Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Scotti, Giuseppe; Bellizia, Davide; Trifiletti, Alessandro; Palumbo, G.

doi:10.1109/tvlsi.2017.2750207

Cited by 38 publications

(36 citation statements)

References 26 publications

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“…Referring to the FMCML logic style, the DFFs are built exploiting both n-Type and p-Type differential pairs, and a level shifter is added to the DFF reported in [12] (see Fig. 1), since to cascade several stages, as in a divider, the common mode voltage of the differential output Q has to be equal to the common mode voltage of the differential input D.…”

Section: Architecture Of the Frequency Dividermentioning

confidence: 99%

“…As shown in [12], we can estimate t CKQ of the FMCML D-latch by applying the time-constant method. Denoting as t pLS , the delay of the level shifter, and with t pLATCH , the delay of the latch core we can write:…”

Section: A Propagation Delaymentioning

confidence: 99%

“…According to [12], t pLATCH can be expressed as the sum of three time constants each representing a section along the signal path of the latch:…”

Section: A Propagation Delaymentioning

confidence: 99%

“…To reduce the supply voltage, different approaches which provide modifications to the conventional MCML have been previously presented [8]- [13]. In particular, the Folded MCML (FMCML) logic style introduced in [12] is particularly suited for low voltage, low power mixed-signal applications [12]- [13].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

Centurelli

Scotti

Trifiletti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110W thus confirming the advantages of the proposed approach.

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Section: Architecture Of the Frequency Dividermentioning

confidence: 99%

Section: A Propagation Delaymentioning

confidence: 99%

“…According to [12], t pLATCH can be expressed as the sum of three time constants each representing a section along the signal path of the latch:…”

Section: A Propagation Delaymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

Centurelli

Scotti

Trifiletti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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“…Today's VLSI technology allows complex circuits to be fabricated in a single semiconductor silicon die with high speed digital logic fitted along with high performance circuits. Though the clock signal frequencies continue to increase but the MOS device sizes will continue to shrivel to Very Deep Sub Micrometer (VDSM) dimensions [3][4][5]. Reducing the device size not only implies shorter channel length but also decreasing device threshold voltages and decreasing inter connects.…”

Section: Introductionmentioning

confidence: 99%

A low noise low power 45 nm technology based simultaneous switching noise (SSN) reduction model for mixed signal VLSI circuits

Seenuvasamurthi¹,

Nagarajan²

2018

AMA_D

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Low noise, low power, minimum delay and smaller area are the prime factors in the current VLSI system design. There are many sources for noises that exhibit various types of noise. Noise in digital ICs can be credited to various sources such as PSN due to circuit switching transition, deviations in device parameters due to process changes, crosstalk noise caused by capacitive coupling among neighbouring circuit interconnects, noise due to charge sharing and charge leakage. Reducing noise is an important factor in VLSI design. This work involves the analysis and reduction of switching noise in the inverter based equivalent circuit model in 45 nm technology. Also, aims to minimize the power utilization, area and delay. Further the noise analysis is extended to half adder circuit and ALU. The noise value observed for the proposed circuit is 140 µV whereas it is 33 mV for the existing circuit. The same circuit is implemented in GDI based half adder and 4 bit ALU. The simulation result show that the proposed model has reported low noise compared with the existing methods.

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An improved current mode logic latch for high‐speed applications

Kumawat

Upadhyay

Sharma

et al. 2019

Int J Communication

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SummaryIn this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.

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Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Cited by 38 publications

References 26 publications

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

A low noise low power 45 nm technology based simultaneous switching noise (SSN) reduction model for mixed signal VLSI circuits

An improved current mode logic latch for high‐speed applications

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