A low noise low power 45 nm technology based simultaneous switching noise (SSN) reduction model for mixed signal VLSI circuits

Abstract

Low noise, low power, minimum delay and smaller area are the prime factors in the current VLSI system design. There are many sources for noises that exhibit various types of noise. Noise in digital ICs can be credited to various sources such as PSN due to circuit switching transition, deviations in device parameters due to process changes, crosstalk noise caused by capacitive coupling among neighbouring circuit interconnects, noise due to charge sharing and charge leakage. Reducing noise is an important factor in VLSI design. This work involves the analysis and reduction of switching noise in the inverter based equivalent circuit model in 45 nm technology. Also, aims to minimize the power utilization, area and delay. Further the noise analysis is extended to half adder circuit and ALU. The noise value observed for the proposed circuit is 140 µV whereas it is 33 mV for the existing circuit. The same circuit is implemented in GDI based half adder and 4 bit ALU. The simulation result show that the proposed model has reported low noise compared with the existing methods.