Recently, several research results have been reported on the integration of electronics with textiles such as the wearable computer and e-textiles [1][2][3]. Most of the previous works were based mainly on conducting threads, yarns, and woven fabrics to implement the interconnections, like the wearable motherboard [4]. For the integration of the IC with fabric, they placed the silicon chip on a flexible plastic board and then integrated the plastic board on the fabric [1][2][3][4]. However, the plastic board is harder than fabric and may generate a stiff feeling in the clothes, not withstanding the long integration process. In addition, its durability is poor due to its different hardness and temperature expansion coefficient.

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We report the successful fabrication of a two-dimensional phase-locked array of vertical-cavity surface-emitting lasers. The array was comprised of more than 160 vertical-cavity surface-emitting lasers of 1.3 μm diameter with a separation of less than 0.1 μm between each lasing element. The array had a 25 μm diameter and each of the elemental lasers was located on a two-dimensional rectangular lattice. The threshold current of the two-dimensional array 45 mA yields a threshold current of 280 μA for an elemental laser. The far-field beam angle of the array was as narrow as 7°, and the spectral purity was found to be good enough to allow for a clear holographic image reconstruction of a holographic memory.

We have investigated the modal properties of two-dimensional phase-locked arrays of vertical cavity surface emitting lasers where the spatial coherency across the aperture comes from the evanescent coupling of the optical fields of the lasers. Typical two-dimensional arrays can be separated into three categories: the periodic array, the circular array, and the centered polygonal array (or concentric circular array). The circular array and centered polygonal array support a more circular symmetric output beam than the periodic array which is a simple two-dimensional extension of a linear array. The farfield pattern of the two-dimensional array has an azimuthal angle dependence such that near zenith, the fundamental array mode shows a single-lobe beam but with increasing angle many sidelohes appear. The highest array mode has a double-lobed far-field pattern near zenith, as in the case of the linear array. The centered polygonal array shows the most circularly symmetric beam pattern of the three which can be controlled by varying the excitation amplitude of the center laser. We have shown that symmetry plays an important role in determining the array mode and that the use of VCSE lasers give a good longitudinal mode selection leading to dynamic single-mode operation. These results can be extended to a quantum box laser array to give better optical beam control.

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It is generally believed that the spatial periodic variation of a dielectric constant ⑀ or refractive index ͱ⑀ can give rise to photonic band gaps. However, through microwave experiments of microstrip lines with a periodic array of holes, we demonstrate that the wave impedance, which depends on ͱ/⑀, is an essential parameter, giving photonic band gaps rather than the refractive index. We explain physically the effect of the magnetic permeability on photonic band gaps, already reported. ͓S1063-651X͑99͒08904-7͔

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.