Communication-efficient hardware acceleration for fast functional simulation

Abstract

This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original testbench.

A timed HW/SW coemulation technique for fast yet accurate system verification

“…They should pay heavy synchronization overhead due to too frequent synchronizations. Kim et al proposed an improved approach that synchronizes simulators at every N'th cycles [12]. Even if it improves emulation performance by reducing the synchronizations, it may result in causality problem if N is chosen too large.…”

Efficient Testbench Code Synthesis for a Hardware Emulator System

“…In [7] the authors propose a methodology to reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting the testbench and moving a part of it into a hardware accelerator.…”

ArChiVED: Architectural checking via event digests for high performance validation

“…BACKGROUND AND RELATED WORK Acceleration and emulation platforms have become increasingly popular over the past decade and today are vital in the validation of complex designs [1,7,9,12]. Modern acceleration platforms can typically reach simulation performances between 10kHz to 1MHz by mapping a design's structural logic description to large arrays of customized processing elements and executing the simulation in a concurrent fashion [4,7,8,17].…”