Efficient Testbench Code Synthesis for a Hardware Emulator System

Mavroidis,; Papaefstathiou, Ioannis

doi:10.1109/date.2007.364405

Cited by 15 publications

(9 citation statements)

References 3 publications

(2 reference statements)

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“…There exist several approaches that confirm the usefulness of replacing simulation with emulation [1], [2]. Also, different commercial simulation acceleration and emulation systems are available from well known vendors (see [8] for a short list).…”

Section: Background and Related Workmentioning

confidence: 96%

Translating behavioral VHDL for emulation

2007

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Emulation is widely used to increase simulation speed. The main problem is that to map it into hardware, the description of the model must be synthesizable. This is not difficult for modules described at lower abstraction levels but almost impossible for behavioral descriptions when using traditional synthesis approaches. In this paper, an overview is given how to use behavioral synthesis principles to convert behavioral VHDL constructs into synthesizable ones. Differences between translation for synthesis and emulation are outlined.

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Section: Background and Related Workmentioning

confidence: 96%

Translating behavioral VHDL for emulation

2007

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“…In contrast, transactionbased acceleration (TBA) [19] is a paradigm in commercial simulation accelerators where the testbench itself has a software-hardware boundary and all interactions with the host are at the transaction-level, thus reducing the amount of data transferred between host and emulation platform. Best results are achieved when large components of the testbench are mapped to hardware [16].…”

Section: Related Workmentioning

confidence: 98%

“…However, in this setup, the testbench still executes in software and communicates with the emulator via a fast bus connector, which is often a bottleneck [16]. In contrast, transactionbased acceleration (TBA) [19] is a paradigm in commercial simulation accelerators where the testbench itself has a software-hardware boundary and all interactions with the host are at the transaction-level, thus reducing the amount of data transferred between host and emulation platform.…”

Section: Related Workmentioning

confidence: 99%

“…As a result, significant portions of a design's state space are left unexplored during simulation. Alternative simulation/execution platforms, namely accelerationbased verification [17], [11], emulation [6], [16] and postsilicon validation [3], [7], are starting to attract more interest because of the performance boost they can provide. Among these, hardware simulation accelerators consist of large arrays of customized ASIC processors designed specifically to simulate basic logic components concurrently.…”

Section: Introductionmentioning

confidence: 99%

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Approximating checkers for simulation acceleration

Mammo¹,

Pidan²,

Nahir³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Simulation-based functional verification is the key validation methodology the industry. The performance of logic simulators, however, is not sufficient to attain acceptable verification coverage on large industrial designs within the time-frame available. Acceleration platforms are a valuable addition to the verification effort in that they can provide much higher coverage in less time. Unfortunately, these platforms do not provide the rich checking capability of software-based simulation.We propose a novel solution to deploy those complex checkers, typical of simulation-based environments, onto acceleration platforms. To this end, checkers must be transformed into synthesizable, compact logic blocks with bug-detection capabilities similar to that of their software counterparts. Our "approximate checkers" trade off logic complexity with bug detection accuracy by leveraging novel techniques to approximate complex software checkers into small synthesizable hardware blocks, which can be simulated along with the design on an acceleration platform. We present a general checker taxonomy, propose a range of approximation techniques based on a checker's characteristic and provide metrics for evaluating its bug detection capabilities.

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“…The testbench still executes in software and communicates with the platform over a bus: in this setup the communication often becomes the bottleneck [13], [10]. Transaction-based acceleration (TBA) [15] attempts to overcome this bottleneck by bundling several interactions between the testbench and the platform into larger, yet less frequent transactions.…”

Section: Contributionsmentioning

confidence: 99%

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Chatterjee¹,

Mammo²,

Lee³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Software-based simulation provides a convenient environment for microprocessor design validation, where a number of complex software checkers are integrated with the simulated design to identify discrepancies between design and specification. Unfortunately, the performance of software-based simulation is vastly inadequate to achieve sufficient coverage for large microprocessor designs with complex microarchitectures. Hence, acceleration and emulation platforms are heavily deployed in the industry for high-performance validation. However, software checkers cannot be directly incorporated into such platforms, forcing designers to craft ad-hoc solutions. Adapting checking solutions for software simulation to acceleration platforms presents the following constraints: i) only a limited number of signals can be monitored per cycle for checking purposes so as to retain acceptable simulation performance, and ii) the overhead of the added checking logic must be minimal.In this work, we explore a novel solution to adapt software-based checkers for individual microarchitectural blocks to acceleration platforms, by leveraging a hybrid approach. Our solution exploits embedded logic and data tracing for post-simulation checking in a synergistic fashion to limit the associated overhead. Embedded logic can be used for synthesized local checkers as well as to compress the traced data and thus limit recording overhead. We analyze several trade-offs associated with checking accuracy and logic / recording overhead for different microarchitectural blocks of an out-of-order superscalar processor design. We strive to provide valuable insights on how to adapt such software checkers to the acceleration environment using our hybrid approach. We find that, by leveraging simple embedded checkers and data compressors (15-25% logic overhead), we can achieve excellent checking accuracy even when aggressively compressing the data for transfer (only 15-25 bits/cycle), and localize bugs up to 5,900 cycles sooner than an architectural-level checker.

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Efficient Testbench Code Synthesis for a Hardware Emulator System

Cited by 15 publications

References 3 publications

Translating behavioral VHDL for emulation

Translating behavioral VHDL for emulation

Approximating checkers for simulation acceleration

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

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