Emulation is widely used to increase simulation speed. The main problem is that to map it into hardware, the description of the model must be synthesizable. This is not difficult for modules described at lower abstraction levels but almost impossible for behavioral descriptions when using traditional synthesis approaches. In this paper, an overview is given how to use behavioral synthesis principles to convert behavioral VHDL constructs into synthesizable ones. Differences between translation for synthesis and emulation are outlined.
In this paper an idea is proposed, how to simulate a large digital system that could not be mapped onto single FPGA, utilizing the sate-of-the-art features of modern reconfigurable devices. Partial reconfiguration of these devices is the feature for the idea described. Methodology of design flow to any platform is proposed and main problems concerning this methodology are highlighted.
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