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Low power is becoming a more crucial performance metrics in system‐on‐chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation. This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero‐delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP‐based SoC system, the average error is estimated at 11.42%.

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In this paper, we propose a power macromodeling technique for digital electronic circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed for register transfer level and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.94%. Our model provides accurate power estimation.

Low-power consumption in three-dimensional integrated circuits (3D IC) design is becoming an important concern that cannot be neglected. The multiple layers/dies are stacked in 3D IC and communicate with each other through-silicon-vias (TSVs) to work as a single device in order to achieve high performance with minimum power dissipation. This paper demonstrates high-level power modeling approach for the power estimation of homogenous integration of Network-on-Chip (NoC)-based mesh architecture in 3D IC design. The preliminary experimental work of power model is divided into two major parts of the design. The first part estimates the power of NoC architecture on each stack separately and the second estimates the power dissipation of the uniformly distributed TSVs and input/output (I/O) pads. The model uses a linear function to estimate the average power dissipation. For an entire IC design, the average power is extracted by simple addition of all power estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 18.03%.

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