Statistical Power Estimation for IP-Based Design

Durrani, Yaseer Arafat; Riesgo, Teresa

doi:10.1109/iecon.2006.348026

Cited by 9 publications

(7 citation statements)

References 14 publications

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“…One important source of error comes from do not consider on the macromodel, the power consumption of interconnects among different IP macro-blocks, and also other factors like glitch activities. For an individual IP block, we measured just 1-2% error in [21], [22]. But for the entire IP-based system with interconnects the error is 20-30%.…”

Section: Resultsmentioning

confidence: 99%

“…Recently we have presented in [21], [22] a macromodel for different IP blocks. The proposed methodology was described as follows: in our static power macromodeling procedure, the sequence of an input stream was generated for a desired input metrics: Pin, Din, Sin, and Tin.…”

Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

“…In our preliminary work, the approach intends to reduce the intensive amount of simulations at a higher abstraction level. We use the same IP blocks presented in [21], [22] and their macromodel information for our IP-based system. Now, instead of simulating every IP block, we applied the Monte Carlo zero delay simulation to the entire test IPbased system.…”

Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

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Architectural Power Estimation Technique for IP-Based System-on-Chip

Durrani

Abril

Riesgo

2007

2007 IEEE International Symposium on Industrial Electronics

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In this paper, we present an architectural power estimation technique for register transfer level. The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

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Section: Resultsmentioning

confidence: 99%

Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

See 1 more Smart Citation

Architectural Power Estimation Technique for IP-Based System-on-Chip

Durrani

Abril

Riesgo

2007

2007 IEEE International Symposium on Industrial Electronics

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“…IP power modeling is currently an important research area in which promising results are being obtained [7]. In some cases, different versions of a given IP functionality are available [2], each one optimized for different requirements (e.g., performance, logic usage, and balance) and therefore exhibiting different power consumption, which should be carefully examined.…”

Section: F Power Management Toolsmentioning

confidence: 99%

Features, Design Tools, and Application Domains of FPGAs

Rodríguez-Andina

Moure

Valdés

2007

IEEE Trans. Ind. Electron.

337

110

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In the past two decades, advances in programmable device technologies, in both the hardware and software arenas, have been extraordinary. The original application of rapid prototyping has been complemented with a large number of new applications that take advantage of the excellent characteristics of the latest devices. High speed, very large number of components, large number of supported protocols, and the addition of readyto-use intellectual property cores make programmable devices the preferred choice of implementation and even deployment in mass production quantities. This paper surveys the advanced features, design tools, and application domains for field-programmable gate arrays (FPGAs). The main characteristics and structure of modern FPGAs are first described to show their versatility and abundance of available design resources. Software resources are also discussed, as they are the main enablers for the efficient exploitation of the design capabilities of these devices. Current application domains are described, such as configurable computing, dynamically reconfigurable systems, rapid system prototyping, communication processors and interfaces, and signal processing. This paper also presents the authors' prospective view of how FPGAs will evolve to enter new application domains in the future.

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“…The temporal correlation captures those features that missed on spatial correlation Sin. In this paper, we continue our previous research in [21], [22] developing power macromodeling technique based on the power estimation methodology using temporal correlation. Our model is LUT based.…”

Section: Introductionmentioning

confidence: 97%

High-level power estimation for digital system

2007

Self Cite

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In this paper, we present a high-level power macromodeling technique at register transfer level (RTL). The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) macroblocks by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

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Statistical Power Estimation for IP-Based Design

Cited by 9 publications

References 14 publications

Architectural Power Estimation Technique for IP-Based System-on-Chip

Architectural Power Estimation Technique for IP-Based System-on-Chip

Features, Design Tools, and Application Domains of FPGAs

High-level power estimation for digital system

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