Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs

Durrani, Yaseer Arafat

doi:10.1142/s0218126618500342

Cited by 5 publications

(7 citation statements)

References 10 publications

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“…1–8 Modern industry control systems impose restrictions on the control signals due to the existing technological limitations. 9–11 In order to meet the requirements of robustness, a number of techniques are applied in the engineering tasks. 12,13 For instance, an application of various nonsquare parameter/polynomial matrices in the inverse model–based control algorithms, including the minimum variance/perfect control procedure, makes such control laws more robust.…”

Section: Introductionmentioning

confidence: 99%

A study on a new criterion for minimum-energy perfect control in the state-space framework

Hunek

Krok

2019

Proceedings of the Institution of Mechanical Engineers, Part I:

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In this article, an advanced study concerning the energy cost of the perfect control algorithm is provided. An application of different nonunique matrix inverses into perfect control law has resulted in remarkable influence on both control and state signals. Following the newly obtained issues, covering the minimum-energy behavior, a new related criterion is proposed here. Based on deterministic norm we can, in a simple way, estimate the crucial energy performance. Simulation examples made in MATLAB/Simulink environment show the high potential of a new approach considered in the article.

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Section: Introductionmentioning

confidence: 99%

A study on a new criterion for minimum-energy perfect control in the state-space framework

Hunek

Krok

2019

Proceedings of the Institution of Mechanical Engineers, Part I:

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“…The power modeling approach of BFT network is discussed in this section. The proposed model further improves these techniques, in the electrical characteristics of the network, and most of the model equations are modified as described below.…”

Section: Power Modeling Methodology For 3d Icmentioning

confidence: 99%

“…Recently, 3D multistacked NoC architecture is introduced to reduce the overall power consumption of the IC. However, most of the work utilizes a simple model to represent the average power dissipation.…”

Section: Related Workmentioning

confidence: 99%

Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

Durrani

2018

Int J Numerical Modelling

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Low‐power consumption and heat dissipation are becoming serious issues in the design process of the 3D integrated circuit (IC). The multiple dies are stacked and communicated through‐silicon vias to work as a single device to achieve high performance with minimum power and heat dissipation. This paper presents the power and thermal modeling approaches for the power/heat estimation of homogenous integration of network‐on‐chip‐based tree architecture in 3D IC design. The preliminary experimental work of power model is divided in 2 major parts of the design. The first part estimates the power of network‐on‐chip tree architecture on each stack/layer separately, and the second estimates the power dissipation of the uniformly distributed through‐silicon vias and input/output pads. The model uses a linear function to estimate the average power dissipation. The thermal model estimates the heat dissipation by using thermal sensors on different sections of the individual layer. For an entire IC design, the average power/thermal is extracted by simple addition of all power/thermal estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 16.29%.

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“…It also reduces the system power with higher performance. A macro-modeling approach for homogeneous integration of NoC based mesh architecture is proposed in [ 23 ]. The first part of the proposed model estimates the average power consumption of the NoC architecture of each core, while the second part estimates the average power of uniformly distributed TSVs.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Our proposed macromodel have 3 parameters TD , SP and SV , instead of correlation parameters S c and T c [ 23 , 26 , 27 ]. S c and T c are spatial and temporal correlations.…”

Section: Power Macromodeling For Ip-based 3d Digital Systemmentioning

confidence: 99%

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Siddiq

Durrani

2022

PLoS ONE

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Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores/stacks/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.

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Power Analysis Approach for NoC-based Homogeneous Stacked 3D ICs

Cited by 5 publications

References 10 publications

A study on a new criterion for minimum-energy perfect control in the state-space framework

A study on a new criterion for minimum-energy perfect control in the state-space framework

Power and thermal modeling approach for homogeneously stacked butterfly fat tree architecture in 3D ICs

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

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