2016
DOI: 10.1016/j.micpro.2016.09.003
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Efficient power analysis approach and its application to system-on-chip design

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Cited by 9 publications
(12 citation statements)
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“…Recently, we have introduced a high-level statistical power modeling approach for the power estimation of 2D ICs of SoC systems in Durrani and Riesgo. 9,19,20 This work is further extended with help of a different approach of high-level power modeling technique, and it is implemented on 3D IC. The results of this model are presented in this section.…”
Section: Resultsmentioning
confidence: 99%
“…Recently, we have introduced a high-level statistical power modeling approach for the power estimation of 2D ICs of SoC systems in Durrani and Riesgo. 9,19,20 This work is further extended with help of a different approach of high-level power modeling technique, and it is implemented on 3D IC. The results of this model are presented in this section.…”
Section: Resultsmentioning
confidence: 99%
“…The experimental results of the power dissipation for NoC‐based homogeneous stacked 3D IC are discussed in this section. Recently, we have proposed power modeling approach for 2D ICs of SoC systems by using test pattern generator in Durrani and Riesgo . We have extended the same work to generate the input sample stimuli that influence the power consumption of the NoC architecture.…”
Section: Resultsmentioning
confidence: 99%
“…We have extended the same work to generate the input sample stimuli that influence the power consumption of the NoC architecture. The average input statistical characteristics of the pattern generator are the transition density TD, the signal probability SP, and the spatiotemporal correlation ST_C as discussed in Durrani and Riesgo . In the characterization phase, the input sequences are randomly generated according to these characteristics with the specified probabilistic range between [0‐1] for the given component of the network.…”
Section: Resultsmentioning
confidence: 99%
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