Statistical Power Estimation For Register Transfer Level

Durrani, Yaseer Arafat; Riesgo, Teresa; Machado, Felipe

doi:10.1109/mixdes.2006.1706635

Cited by 11 publications

(9 citation statements)

References 22 publications

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“…All this process is divided in two steps. In the first one, the metrics of the inputs/outputs (I/O) sequences were computed by our GA [19], [20] and the power function was obtained using PIP_avg in "(1)". The interpolation scheme [12], [13] can be applied (to improve power sensitivity concept), if the input metrics do not match based on their characteristics.…”

Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

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Architectural Power Estimation Technique for IP-Based System-on-Chip

Durrani

Abril

Riesgo

2007

2007 IEEE International Symposium on Industrial Electronics

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In this paper, we present an architectural power estimation technique for register transfer level. The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) components by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

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Section: Proposed Macromodeling Methodologymentioning

confidence: 99%

“…Once the input metrics are selected, the input sequences are computed by our GA in [19], [20]. Monte Carlo zero delay simulation technique [8] is performed and for the IP macroblocks, the power dissipation is obtained by our macromodel function.…”

Section: Introductionmentioning

confidence: 99%

Architectural Power Estimation Technique for IP-Based System-on-Chip

Durrani

Abril

Riesgo

2007

2007 IEEE International Symposium on Industrial Electronics

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“…It computes the Markov chain that results from the interaction of the input probability distribution IP-based blocks dictated by its finite state machine (FSM). The more details of our algorithm can be found in [19], [20]. Monte Carlo zero delay simulation technique [8] is performed and for the IP macro-blocks, the power dissipation is obtained by our macromodel function.…”

Section: Power Macromodelingmentioning

confidence: 99%

High-level power estimation for digital system

2007

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In this paper, we present a high-level power macromodeling technique at register transfer level (RTL). The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) macroblocks by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

show abstract

“…Once the I/O metrics are selected, the I/O sequences are computed by our genetic algorithm (GA) [19], [20]. Monte Carlo zero delay simulation technique [8] is performed and for the IP macro-blocks, the power dissipation is predicted by our macromodel function.…”

Section: IImentioning

confidence: 99%

“…All this process we can be divided in two steps. In the first one, the metrics of the I/O sequences are computed by our GA [19], [20] and the power dissipation is predicted using Pavg in "(1)". The interpolation scheme [12], [13] can be applied (to improve power sensitivity concept), if the input metrics do not match based on their characteristics.…”

Section: IImentioning

confidence: 99%

Power Macromodeling for IP Modules

Durrani

Riesgo

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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In this paper, we propose a power macromodeling technique for digital electronic circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero delay simulation is performed for register transfer level and the power dissipation is predicted by a macromodel function. In experiments with IP macro-blocks, the results are effective and highly correlated, with an average error of 1.94%. Our model provides accurate power estimation.

show abstract

Statistical Power Estimation For Register Transfer Level

Cited by 11 publications

References 22 publications

Architectural Power Estimation Technique for IP-Based System-on-Chip

Architectural Power Estimation Technique for IP-Based System-on-Chip

High-level power estimation for digital system

Power Macromodeling for IP Modules

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