2006 13th IEEE International Conference on Electronics, Circuits and Systems 2006
DOI: 10.1109/icecs.2006.379649
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Abstract: In this paper, we propose a power macromodeling technique for digital electronic circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero dela… Show more

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Cited by 8 publications
(7 citation statements)
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References 19 publications
(24 reference statements)
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“…One important source of error comes from do not consider on the macromodel, the power consumption of interconnects among different IP macro-blocks, and also other factors like glitch activities. For an individual IP block, we measured just 1-2% error in [21], [22]. But for the entire IP-based system with interconnects the error is 20-30%.…”
Section: Resultsmentioning
confidence: 99%
See 2 more Smart Citations
“…One important source of error comes from do not consider on the macromodel, the power consumption of interconnects among different IP macro-blocks, and also other factors like glitch activities. For an individual IP block, we measured just 1-2% error in [21], [22]. But for the entire IP-based system with interconnects the error is 20-30%.…”
Section: Resultsmentioning
confidence: 99%
“…Recently we have presented in [21], [22] a macromodel for different IP blocks. The proposed methodology was described as follows: in our static power macromodeling procedure, the sequence of an input stream was generated for a desired input metrics: Pin, Din, Sin, and Tin.…”
Section: Proposed Macromodeling Methodologymentioning
confidence: 99%
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“…We have observed that the same methodology works as well for different IP macro-blocks such as array multipliers, comparators, delay elements (shift registers), adders in terms of the statistical knowledge of their primary inputs/outputs. Recently we have presented in [21], [22] a macromodel for different IP blocks. The proposed methodology was described as follows: in our static power macromodeling procedure, the sequence of an input stream was generated for a desired input metrics: Pin, Din, Sin, and Tin.…”
Section: Proposed Macromodeling Methodologymentioning
confidence: 99%
“…The temporal correlation captures those features that missed on spatial correlation Sin. In this paper, we continue our previous research in [21], [22] developing power macromodeling technique based on the power estimation methodology using temporal correlation. Our model is LUT based.…”
Section: Introductionmentioning
confidence: 97%