High-Level Power Analysis for Intellectual Property-Based Digital Systems

Durrani, Yaseer Arafat; Riesgo, Teresa

doi:10.1166/jolpe.2013.1283

Cited by 7 publications

(6 citation statements)

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“…Recently, we have introduced a power macromodel for different IP blocks in the literature. 13,14 In this section, the result of extended work for high-level power modeling approach is presented. The experimental work is evaluated on IP core-based SoC system, shown in Figure 5.…”

Section: Resultsmentioning

confidence: 99%

“…The main advantage of power macromodel is that it can provide fast and accurate estimates; thus, it helps designers to explore different complex blocks in real time. We opted for a simple function with low-order polynomial dependency on f (⋅) in Equation 13. The estimated power P SoC_system in Equation 9 is compared with the simulated power estimation P Simulated (taken from the power simulator) to evaluate the accuracy of the power macromodel function.…”

Section: Resultsmentioning

confidence: 99%

“…Similarly, the paper has implemented genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Previously, we introduced accurate power macromodeling technique [13][14][15][16] that is implemented on IPbased digital test systems. In this work, we further continue this research and developed 2 separate statistical macromodels that estimate power for different IP cores and buses of the SoC-based test system.…”

Section: Paper Overview and Contributionsmentioning

confidence: 99%

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Power macromodeling technique and its application to SoC‐based design

Durrani

Riesgo

2016

Int J Numerical Modelling

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Low power is becoming a more crucial performance metrics in system‐on‐chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation. This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero‐delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP‐based SoC system, the average error is estimated at 11.42%.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Paper Overview and Contributionsmentioning

confidence: 99%

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Power macromodeling technique and its application to SoC‐based design

Durrani

Riesgo

2016

Int J Numerical Modelling

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“…They improve the performance parameters of 3D IC design. It also allows the power management of budget during the initial design phases [ 1 ].…”

Section: Introductionmentioning

confidence: 99%

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Siddiq

Durrani

2022

PLoS ONE

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Low-power consumption has been always a crucial design constraint for an efficient intellectual property based three-dimensional multi-core system that cannot be ignored easily. As the complexity increases due to the number of cores/stacks/ layers in 3D digital systems, the challenges to handle power can be more difficult at a high abstraction level. Therefore, the low-power approach gives designers an opportunity to estimate and optimize the power consumption in the early stages of design phases. The accurate power estimation through the macro-modeling approach at high-level reduces the risk of redesign cycle and turn-around time. In this research, we have presented an improved statistical macro-modeling approach that estimates power through statistical characteristics of randomly generated input patterns by using Biogeography Based Optimization. These input patterns propagate signals into an IP-based 3D digital test system. In experiments, the test system is based on four 8 to 32- bits heterogeneous cores. The response of the power is monitored by applying the well-known Monte Carlo Simulation technique. The entire power estimation method is performed in two major steps. First, the average power is estimated for an IP-based individual core. Second, the average power for bus-based Through-Silicon-Via is estimated. Finally, the cores and B-TSVs are integrated together to construct a 3D system. Then the average power for complete test systems is estimated. The experimental results of the statistical power macro-model are compared with the commercial Electronic Design Automation power simulator at the operating frequency of 100 MHz. The average percentage error of the test system is calculated as 8.65%. For the validation of these results, the statistical error analysis is additionally performed and reveals that our proposed macro-model is accurate in terms of percentage of error with a feasible amount of time.

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“…These EDA tools improve the performance metrics in IC design. Earlier design analysis has ignored the redesigning procedure and it also manages the power requirement during the initial design phase [2]. Due to the evolutionary growth of a system's complexity, verification of system is a very time-consuming procedure; therefore, power and performance analysis are very essential for reducing the turnaround time.…”

Section: Introductionmentioning

confidence: 99%

Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm

Siddiq¹,

Durrani²

2021

Turkish Journal of Electrical Engineering and Computer Sciences

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Low-power consumption is becoming a crucial concern that cannot be neglected in system-on-chip (SoC) designs. Low-power solutions help designers to provide a powerful methodology to analyze, estimate, and optimize today's power concerns. Early estimation of power at a high level reduces the redesign cycle and turn-around time.Power dissipation is a function of input patterns and their characteristics. This paper describes a power estimation technique by using predefined statistical characteristics-based input patterns, which gives the average power dissipation of individual intellectual property (IP) blocks and interconnects/buses in an SoC system design. During the power estimation phase, the discrete water cycle algorithm is implemented to generate optimized input patterns. Then Monte-Carlo zero-delay simulation approach is used for each individual IP block and buses at a high level. Total system power is the simple addition of average powers of IP blocks and buses. In experiments of entire IP-based SoC system with buses, our modified macromodel gives an average error of 7.91%. Accuracy of the proposed model is improved as compared to our previous model.

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High-Level Power Analysis for Intellectual Property-Based Digital Systems

Cited by 7 publications

References 0 publications

Power macromodeling technique and its application to SoC‐based design

Power macromodeling technique and its application to SoC‐based design

Efficient power macromodeling approach for heterogeneously stacked 3d ICs using Bio-geography based optimization

Efficient power macromodeling approach for an IP-based SoC system using discrete water cycle algorithm

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