Power estimation for intellectual property-based digital systems at the architectural level

Durrani, Yaseer Arafat; Riesgo, Teresa

doi:10.1016/j.jksuci.2014.03.005

Cited by 12 publications

(10 citation statements)

References 16 publications

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“…modelling expandability: it corresponds to the capability of a power model to provide power estimation of a composite system. Modelling expandability has been shown in [74], where the table-based power models of IP-based modules were extended and connected together to get the power consumption of a composite system, such as a System-on-Chip device. The same conclusion can be drawn for neural networks [105], [10].…”

Section: E Analysis and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Nasser

Lorandel

Prévotet

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Power consumption constitutes a major challenge for electronics circuits. One possible way to deal with this issue is to consider it very soon in the design process in order to explore various design choices. A typical design flow often starts with a high-level description of a full system, which imposes to provide accurate models. Power modelling techniques can be employed, providing a way to find a relationship between power and other metrics. Furthermore, it is also important to consider efficient power characterization techniques. The role of this paper is, first, to provide an overview of RTL to transistor level power modelling and estimation techniques for FPGAs and ASICs devices. Second, it aims at proposing a classification of all approaches according to defined metrics, which should help designers in finding a particular method for their specific situation, even if no common reference is defined among the considered works. Index Terms-Power consumption, power modelling, power estimation, high-level power estimation, FPGA, ASIC, tools.. Antifuse Technology (e.g., Actel TM , Quicklogic TM): an antifuse remains in a high-impedance state until it is programmed into a low-impedance or "fused" state (Figure 9.18). This technology can be used only once on one-time programmable (OTP) devices; it is less expensive than the RAM technology.

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Section: E Analysis and Discussionmentioning

confidence: 99%

“…Although this is a very good improvement in terms of estimation accuracy, additional attributes and computations are required. The authors in [74] extended the work of [73]. They demonstrated the use of the table-based method for a full system power estimation and proved the scalability of the method.…”

Section: B Table-based Power Modelling Techniquementioning

confidence: 91%

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Nasser

Lorandel

Prévotet

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Our current work is inspired from [1], and in the continuity of [5] and [6]. In [1] a power macro-model for (Intellectual Property) IP power estimation is proposed that is based on lookup table (LUT) power models. The IP power model used to estimate the power consumption of an IP-based digital system which is based on signal statistics propagation.…”

Section: Related Workmentioning

confidence: 99%

Power modeling on FPGA

Nasser¹,

Prévotet²,

Hélard³

2018

Proceedings of the 15th ACM International Conference on Computing Frontiers

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Today reducing power consumption is a major concern especially when it concerns small embedded devices. Power optimization is required all along the design flow but particularly in the first steps where it has the strongest impact. In this work, we propose new power models based on neural networks that predict the power consumed by digital operators implemented on Field Programmable Gate Arrays (FPGAs). These operators are interconnected and the statistical information of data patterns are propagated among them. The obtained results make an overall power estimation of a specific design possible. A comparison is performed to evaluate the accuracy of our power models against the estimations provided by the Xilinx Power Analyzer (XPA) tool. Our approach is verified at systemlevel where different processing systems are implemented. A mean absolute percentage error which is less than 8% is shown versus the Xilinx classic flow dedicated to power estimation.

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“…Design reuse is a key advantage of this method. In [5], a power estimation technique at RTL is proposed. It enables the power estimation of a macro (e.g.…”

Section: Related Workmentioning

confidence: 99%

Dynamic power estimation based on switching activity propagation

Nasser

Prévotet

Heiard

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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A new power estimation approach based on the decomposition of a digital system into basic operators is presented. This approach aims to estimate the energy consumption at early design phases of digital blocks implemented on FPGAs. Each operator has its own model which estimates the switching activity and the power consumption. By interconnecting several operators, statistical information is then propagated to provide a global power estimation of a given system. A simple sum of the power dissipation contribution of each operator is enough to compute the total power consumption. This is performed by taking into account the switching activities relative to a given input pattern. Earlier, faster and more flexible power analysis for system designers are the advantages. This approach has been evaluated in a use-case application. The preliminary results indicate a promising speed-up of the design process and an error which is less than 8.0% compare to the classical power estimation tools.

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Power estimation for intellectual property-based digital systems at the architectural level

Cited by 12 publications

References 16 publications

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey

Power modeling on FPGA

Dynamic power estimation based on switching activity propagation

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