Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

In this letter, we propose a method to enhance resistive switching properties in SiCN-based conductive-bridge resistive switching memory (CBRAM) devices by inserting a thin Al2O3 layer between the SiCN resistive switching layer and the TiN bottom electrode. Compared with the Cu/Ta/SiCN/TiN single-layer device, the Cu/Ta/SiCN/Al2O3/TiN double layer device exhibits uniform resistive switching, long stable endurance cycles (>1.6 × 104), and stable retention (104 s) at 125 °C. These substantial improvements in the resistive switching properties are attributed to the location of the formation and rupture of conductive filaments that can be precisely controlled in the device after introducing the Al2O3 layer. Moreover, a multilevel resistive switching characteristic is observed in the Cu/Ta/SiCN/Al2O3/TiN double layer CBRAM device. The distinct six-level resistance states are obtained in double layer devices by varying the compliance current. The highly stable retention characteristics (>104) of the Cu/Ta/SiCN/Al2O3/TiN double layer device with multilevel resistance states are also demonstrated.

The mechanism of forming-free bipolar resistive switching in a Zr/CeO x /Pt device was investigated. High-resolution transmission electron microscopy and energy-dispersive spectroscopy analysis indicated the formation of a ZrO y layer at the Zr/CeO x interface. X-ray diffraction studies of CeO x films revealed that they consist of nano-polycrystals embedded in a disordered lattice. The observed resistive switching was suggested to be linked with the formation and rupture of conductive filaments constituted by oxygen vacancies in the CeO x film and in the nonstoichiometric ZrO y interfacial layer. X-ray photoelectron spectroscopy study confirmed the presence of oxygen vacancies in both of the said regions. In the low-resistance ON state, the electrical conduction was found to be of ohmic nature, while the high-resistance OFF state was governed by trap-controlled space charge-limited mechanism. The stable resistive switching behavior and long retention times with an acceptable resistance ratio enable the device for its application in future nonvolatile resistive random access memory (RRAM).

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