3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS2 memristor arrays are reported. The MoS2 memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS2 memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS2 layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

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Memtransistors that combine the properties of transistor and memristor hold significant promise for in-memory computing. While superior data storage capability is achieved in memtransistors through gate voltage-induced conductance modulation, the lateral device configuration would not only result in high write bias, which compromises the power efficiency, but also suffers from unsuccessful memory reset that leads to reliability concerns. To circumvent such performance limitations, an advanced physics-based model is required to uncover the dynamic resistive switching behavior and deduce the key driving parameters for the switching process. This work demonstrates a self-consistent physics-based model which incorporates the often-overlooked effects of lattice temperature, vacancy dynamics, and channel electrostatics to accurately solve the interaction between gate potential, ions, and carriers on the memristive switching mechanism. The completed model is carefully calibrated with an ambipolar WSe2 memtransistor and hence enables the investigation of the carrier polarity effect (electrons vs holes) on vacancy transport. Nevertheless, the validity of the model can be extended to different materials by a simple material-dependent parameter modification. Building upon the existing understanding of Schottky barrier height modulation, our study reveals three key insightsleveraging threshold voltage shifts to lower write bias; optimizing lattice temperature distribution and read bias polarity to achieve successful memory state recovery; engineering contact work function to overcome the detrimental parasitic current flow in short channel ambipolar memtransistors. Therefore, understanding the significant correlation between the switching mechanisms, different material systems, and device structures allows performance optimization of operating modes and device designs for future memtransistors-based computing systems.

An ultra-thin (15 nm) InGaAs nanomembrane field-effect phototransistor is transferred entirely from a rigid InP substrate onto a flexible SU-8 on a polydimethylsiloxane substrate. The transferred InGaAs device exhibits wide-band spectral response tunability up to 1.8 µm, from the visible to near-infrared light. Using an epitaxial lift-off process of InGaAs-on-InP MOSHEMT, the transferred device is inverted with a fully exposed channel for photosensitivity enhancement, while retaining three terminals for photocurrent amplification and modulation. The photocurrent can be tuned ∼5 orders over a gate bias range of 6 V. On-state photo-responsivities of 350 A/W to 15 A/W for 0.6 µm and 1.8 µm of light, respectively, is measured, ∼2 × higher than existing silicon and III-V photodetectors. Furthermore, the device shows no electrical performance degradation when flexed down to 10-cm radius, demonstrating suitability for conformal surface sensor applications.

A ferroelectric field-effect transistor (FeFET), capable of logic and memory functionalities in a single device, is a promising three-terminal memtransistor that enables high-performance in-memory computing for non Von Neumann architectures. Among all HfO2-based ferroelectric materials, HfZrO2 (HZO) has attracted the most attention due to the low process temperature of ≤500 °C; however, it has relatively weak polarization. Many prior works claimed that the way to improve HZO-based FeFET characteristics is to enhance HZO ferroelectric properties, while they did not account for the fundamental compromise on dielectric breakdown strength (BDS), transistor ON/OFF current (I ON/I OFF) ratio, and memory window (MW) due to the enhanced polarization. In this work, we propose an approach for controlling the ferroelectric orthorhombic phase (O phase) and the corresponding polarization in optimal value by engineering both the surface morphology and stress of HZO layer by a thermal expansion mismatch with a TiN/W stacked capping layer, to improve the BDS, I ON/I OFF ratio, and MW. Through electrode surface optimization and stress memorization we achieved an 18% HZO ferroelectricity increase with a high BDS value of ≥4.8 MV/cm. Our optimized FeFET shows good electrical characteristics and supports operation in an identical pulse programming (IPP) mode, showing good potentiation and depression nonlinearity (−0.84 and −2.04) with an asymmetry factor of 1.2. A simulation based on the proposed FeFET array demonstrates the high potential of application in an artificial neural network (ANN).

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