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A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slottype floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half-or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.

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In the recent years, de-embedding method of "open-short", and "open-thru" with dummy DUTs are mostly used for on-wafer devices. This paper shows a method, called L-2L, with two metal lines or transmission lines. One is two times the length of the other one. Based on the measurement data of two lines, PAD parasitics and scalable length model with certain width are obtained by L2L. Furthermore, the tape-out DUT numbers for the de-embedding are extremely minimized to 2. The applications for inductors by 65 nm Low-K Si-based process and 0.18 µm FSG Si-based process, and for 0.13 µm transmission lines are also shown for benchmark in this paper.

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