By utilizing a differential tunable active inductor for the LC-tank, a wide tuning-range CMOS voltage-controlled oscillator (VCO) is presented. In the proposed circuit topology, the coarse frequency tuning is achieved by the tunable active inductor, while the fine tuning is controlled by the varactor. Using a 0.18-m CMOS process, a prototype VCO is implemented for demonstration. The fabricated circuit provides an output frequency from 500 MHz to 3.0 GHz, resulting in a tuning range of 143% at radio frequencies. The measured phase noise is from 101 to 118 dBc/Hz at a 1-MHz offset within the entire frequency range. Due to the absence of the spiral inductors, the fully integrated VCO occupies an active area of 150 300 m 2 .

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In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-m CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP 3 of 8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 W, respectively.

In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-m CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of 118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and 114 dBc/Hz, respectively. Index Terms-Capacitive feedback, forward body bias (FBB), ultra-low power, ultra-low voltage, voltage-controlled oscillators (VCOs).

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A built-in self-test (BIST) technique suitable for RF low-noise amplifiers (LNAs) is presented in this paper. With fully integrated amplitude detectors and logarithmic amplifiers, the BIST module can be employed as a generic platform for gain extraction of the device-under-test (DUT) without expensive testing instruments, while maintaining a reasonable hardware overhead and minimum loading effects to the DUT. Using a 0.18-m CMOS process, a 5-GHz variable-gain LNA with the proposed BIST module is implemented. Based on the experimental results, on-chip gain extraction of the LNA has been demonstrated with an error less than 1 dB for various gain modes. The additional chip area required for the BIST functionality measures 0.042 mm 2 , which is considerably small compared with the physical size of the RF amplifiers.

In the proposed PLL architecture, the phase/frequency Implemented in a standard 0.18-um CMOS process, a 0.5-V detector (PFD) is implemented by conventional DFF-based 1.9-GHz low-power phase-locked loop (PLL) is presented.topology [1] due to the relatively low operating speed. TheDue to the use of the forward-body-bias technique, the thre-proposed charge pump is shown in Fig. 3. With the reduced shold voltage of the MOSFETs is effectively reduced, makinlg supply voltage, stacking transistor stages should be prevented.