A Wide Tuning-Range CMOS VCO With a Differential Tunable Active Inductor

Lu, Liang-Hung; Hsieh, Hsieh-Hung; Liao, Yu-Te

doi:10.1109/tmtt.2006.880646

Cited by 140 publications

(61 citation statements)

References 15 publications

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“…6, the quality factor of the solenoid inductor is smaller than that of the spiral inductor. Also, it is smaller than that of the active inductor in [5]. Thus, the phase noise performance of this work is inferior to those of [5] and [6].…”

Section: Resultsmentioning

confidence: 81%

“…Also, it is smaller than that of the active inductor in [5]. Thus, the phase noise performance of this work is inferior to those of [5] and [6]. According to our simulation, the phase noise of the DCO with the proposed solenoid inductor at the output frequency of 5 GHz is degraded by about 4 dB and 2 dB compared with those using the spiral inductor and active inductor, respectively.…”

Section: Resultsmentioning

confidence: 82%

“…9 shows the schematic of the active inductor. It is a differentially configured gyrator-C active inductor [5]. The inductance (L eq ) of the active inductor can be tuned by varying G ds5 , G ds7 , G ds9 , G ds11 , and G dsGCB , where G ds5 , G ds7 , G ds9 and G ds11 are the drain conductances of M 5 , M 7 , M 9 and M 11 in Fig.…”

Section: Wide Range Dco With On-chip Solenoid Inductormentioning

confidence: 99%

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A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

Park¹,

Kim²,

Lee³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a wide band, fineresolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 µm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 µm process and the die area of the solenoid inductor is 0.013 mm 2 . The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

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Section: Resultsmentioning

confidence: 81%

Section: Resultsmentioning

confidence: 82%

Section: Wide Range Dco With On-chip Solenoid Inductormentioning

confidence: 99%

See 1 more Smart Citation

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

Park¹,

Kim²,

Lee³

2013

JSTS:Journal of Semiconductor Technology and Science

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“…Figure 12(a) shows the schematic of the active inductor. It is a differentially configured gyrator-C active inductor [9]. Figure 12(b) shows the schematic of the active inductor control bank.…”

Section: The Three-step Tdcmentioning

confidence: 99%

An all digital PLL with an active inductor DCO for LTE applications in 0.13 μm CMOS

Park

et al. 2011

Analog Integr Circ Sig Process

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In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range and to operate at a lowpower, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm 2 using 0.13 lm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.Keywords All-digital phase-locked loop (ADPLL) Á Time-to-digital converter (TDC) Á Phase-interpolator Á Time amplifier Á Wide tuning range frequency Á Active inductor Á Fine-resolution Á Digitally controlled oscillator (DCO)

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“…Practically the tuning rang of VCO is low and these makes them unsuitable for wideband applications. By utilizing switched capacitors [1], [2] and switched inductors [3], [4], tuning rang of wide frequency can be obtained. The disadvantages are: enlarging the chip area and complexity of control mechanism.…”

Section: Introductionmentioning

confidence: 99%