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By utilizing a differential tunable active inductor for the LC-tank, a wide tuning-range CMOS voltage-controlled oscillator (VCO) is presented. In the proposed circuit topology, the coarse frequency tuning is achieved by the tunable active inductor, while the fine tuning is controlled by the varactor. Using a 0.18-m CMOS process, a prototype VCO is implemented for demonstration. The fabricated circuit provides an output frequency from 500 MHz to 3.0 GHz, resulting in a tuning range of 143% at radio frequencies. The measured phase noise is from 101 to 118 dBc/Hz at a 1-MHz offset within the entire frequency range. Due to the absence of the spiral inductors, the fully integrated VCO occupies an active area of 150 300 m 2 .

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In this paper, ultra-low-voltage circuit techniques are presented for CMOS RF frontends. By employing a complementary current-reused architecture, the RF building blocks including a low-noise amplifier (LNA) and a single-balanced down-conversion mixer can operate at a reduced supply voltage with microwatt power consumption while maintaining reasonable circuit performance at multigigahertz frequencies. Based on the MOSFET model in moderate and weak inversion, theoretical analysis and design considerations of the proposed circuit techniques are described in detail. Using a standard 0.18-m CMOS process, prototype frontend circuits are implemented at the 5-GHz frequency band for demonstration. From the measurement results, the fully integrated LNA exhibits a gain of 9.2 dB and a noise figure of 4.5 dB at 5 GHz, while the mixer has a conversion gain of 3.2 dB and an IIP 3 of 8 dBm. Operated at a supply voltage of 0.6 V, the power consumptions of the LNA and the mixer are 900 and 792 W, respectively.

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-m CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a 3-dB bandwidth of 9 GHz. With a 2 31 1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10 12 are 300 and 10 mV pp , respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68 0.8 mm 2 where the active circuit area only occupies 0.32 0.6 mm 2 .

Frequency dividers and VCOs are the most critical building blocks for the implementation of high-frequency signal sources that are widely used in wireline and wireless communication systems. In this paper, circuit topologies are presented to improve the performance of these high-frequency components. For the frequency divider, the proposed g m -enhancement technique incorporates the series and shunt inductive peaking in the resonator design. With the regenerative mechanism in the injection-locked frequency divider, a wide locking range can be achieved without using varactors for frequency tuning. As for the VCO, a balanced architecture is proposed for low phase noise while relaxing the stringent requirement on the start-up conditions at higher frequencies. Both of the circuits are designed and fabricated in a 0.18µm CMOS process.Injection-locked frequency dividers loaded with on-chip resonators are used to provide high-speed frequency division at low power consumption [1]. However, the limited locking range due to the high-Q resonators makes it difficult to cover the frequency tuning range of the VCOs under process and temperature variations. Tuning the free-running frequency with the varactors at the cost of a more complicated controlled mechanism when the divider is integrated in a system can extend the operating range of the divider. Alternatively, a regenerative divider with inductive loads presents an enhanced input bandwidth [2]. Due to the use of the mixer in the regenerative loop, higher power consumption is typically required. To overcome the design limitations, a g menhancement technique to increase the loop gain for regenerative frequency division is proposed. Figure 30.4.1 shows the block diagram of a regenerative divider that consists of a feedback loop with a mixer and a band-pass filter. As the input signal ω in mixes with the feedback signal ω in /2, frequency components of 3ω in /2 and ω in /2 are generated at the output of the mixer. With the selectivity of the LC-tank, frequency division is achieved provided that the open-loop gain for the component at ω in /2 exceeds unity. Consequently, it is desirable to maximize theloop-gain in the circuit design for wideband operations. A conventional circuit topology of the frequency divider is shown in Fig. 30.4.1, where the switching transistor M 1 acts as the mixer and the cross-coupled pair with the LC-tank forms the feedback loop [3]. As the RF signal applies at the gate, M 1 can be treated as a passive drainpumped mixer [4]. By biasing the gate voltage higher than the threshold voltage, the transconductance of M 1 is a nonlinear function of the drain voltage V ds . To maximize the effective transconductance g m,eff for an enhanced conversion gain, a series inductive peaking technique is adopted. By inserting the inductor L s in series with M 1 , the effective drain voltage V ds,eff increases as long as ω s >√[(ω LO 2 +ω d 2 )/2], where ω s =(L s C d ) -1 and ω d =(R ds C d ) -1 . Note that the maximum V ds,eff is obtained with ω s =√(ω LO 2 +ω d 2 )...

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a -boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-m CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured in 1 dB and IIP 3 are 18 and 8.6 dBm, respectively. For the LNA with a -boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.

In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-m CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of 118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and 114 dBc/Hz, respectively. Index Terms-Capacitive feedback, forward body bias (FBB), ultra-low power, ultra-low voltage, voltage-controlled oscillators (VCOs).