A V-Band Divide-by-Three Injection-Locked Frequency Divider in 28 nm CMOS

Hsieh, Hsieh-Hung; Liu, Yi-Hsuan; Yeh, Tzu-Jin; Jou, Chewn-Pu; Hsueh, Fu-Lung

doi:10.1109/lmwc.2012.2225603

Cited by 11 publications

(7 citation statements)

References 6 publications

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“…In addition to low power consumption, the main design considerations for a VCO include frequency tuning range, output power and phase noise . Furthermore, the main design considerations for the first‐stage frequency divider include power dissipation, frequency locking range (LR) and output power . For millimeter‐wave PLL design, one of the basic requirements is a robust VCO together with properly arranged dividers, whose operation LR need to be overlapped with each other .…”

Section: Introductionmentioning

confidence: 99%

“…[3][4][5][6] Furthermore, the main design considerations for the firststage frequency divider include power dissipation, frequency locking range (LR) and output power. [7][8][9] For millimeterwave PLL design, one of the basic requirements is a robust VCO together with properly arranged dividers, whose operation LR need to be overlapped with each other. [10][11][12] In addition, in order to cover the frequency shift of the VCO due to the process variation, a wide frequency LR characteristic is a must for the first-stage frequency divider.…”

Section: Introductionmentioning

confidence: 99%

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77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

Lin

Lan

Wang

et al. 2018

Micro & Optical Tech Letters

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The design and implementation of a 77 GHz phase‐locked loop (PLL) for automobile radar system in 90 nm CMOS technology is demonstrated. To enhance the operation frequency range of the voltage‐controlled oscillator in the PLL, reversely tunable LC source degeneration technique is adopted. To improve the frequency locking range of the divide‐by‐3 injection‐locked frequency divider in the PLL, a parallel inductor is used to parallel resonate the parasitic capacitance of the cross‐coupled transistors. In addition, a phase and frequency detector with enhanced D flip flops is used to effectively reduce the dead zone. The PLL consumes only 49.6 mW and exhibits an operation range of 2.4 GHz (76.8∼79.2 GHz) and reference sidebands of <–56 dBc. The chip area of the PLL is only 0.656 mm2 excluding the test pads.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

Lin

Lan

Wang

et al. 2018

Micro & Optical Tech Letters

View full text Add to dashboard Cite

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“…dB which agrees well with the theoretical value for a noise free divide-by-4 ILFD. Table 6-1 summaries the performance of proposed ILFD and compares it with the other state-of-arts mm-wave frequency ILFDs with high division ratio [16][17][18][21][22][23].…”

Section: Resultsmentioning

confidence: 99%

“…Many efforts have been made to improve the locking range of divide-by-2 ILFD, such as using the shunt peaking technique [19], and frequency tracking technique [20]. Recently, the ILFDs with division ratio larger than 2 have been reported, for instance, the divide-by-3 ILFD in [21], the divide-by-4 ILFD in [22], and the divide-by-5 ILFD in [23]. However, comparing to divide-by-2 ILFD, the locking range of high division ratio ILFD is much narrower due to the low power level of high order harmonic components [73].…”

Section: Discussionmentioning

confidence: 99%

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Design of voltage-controlled oscillators and frequency dividers for 60 GHZ wireless communication applications

Zou¹

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Frequency tuning hysteresis of a dual‐resonance divide‐by‐three cross‐coupled injection‐locked frequency divider

Jang

Jian

Hsue

2018

IET Microwaves, Antennas & Propagation

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This paper studies the frequency tuning effect on the locking range property of a dual‐resonance 3:1 injection‐locked frequency divider (ILFD) fabricated in a foundry 0.18 μm BiCMOS process. The ILFD architecture is based on a capacitive cross‐coupled oscillator in conjunction with a resistor‐degraded dual‐resonance resonator for the locking range improvement. At a power consumption of 5.26 mW and at injection power of Pinj = 0 dBm the locking range from the measurement is from 6.2 to 12.6 GHz (68.09%). The frequency tuning range of the free‐running ILFD shows a frequency tuning hysteresis effect; at low input power level the locking range shows bipolar locking ranges and at high injection power the locking range is independent of the measured voltage tuning direction.

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A V-Band Divide-by-Three Injection-Locked Frequency Divider in 28 nm CMOS

Cited by 11 publications

References 6 publications

77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

77 GHz phase‐locked loop for automobile radar system in 90‐nm CMOS technology

Design of voltage-controlled oscillators and frequency dividers for 60 GHZ wireless communication applications

Frequency tuning hysteresis of a dual‐resonance divide‐by‐three cross‐coupled injection‐locked frequency divider

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