We present an ultra-low-power Bluetooth lowenergy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F 2 digital power amplifier (PA), featuring high efficiency. Low 1/ f DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (∼10 Gsamples/s) with intermediate frequency placed beyond 1/ f noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE. Index Terms-All-digital PLL (ADPLL), Bluetooth low energy (BLE), digitally controlled oscillator (DCO), discrete-time (DT) receiver (RX), Gaussian frequency shift keying (GFSK), intermediate frequency (IF), Internet of Things (IoT), low-power (LP) transceiver (TRX), matching network, transmit/receive (T/R) switch, transmitter (TX).

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1][2][3][4][5]. Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes.In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offsetcancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil f T -doubler output buffer. The block diagram and experimental setup are shown in Fig. 8.4.1. The capacitance of the off-chip GaAs PIN photodetector (PD), which is wire-bonded to the CMOS receiver, is 100fF with 0.4A/W responsivity. The two optical receivers have identical designs except for the LA, in which two different inductive peaking techniques, conventional and sharedinductor, are designed and fabricated on the same die in 28nm CMOS technology. Figure 8.4.2 shows the circuit schematics of the pseudo-differential CMOS pushpull TIA with series-peaking inductors. The CMOS push-pull TIA has good signal gain and input-referred noise at low supply voltage because of current re-use of NMOS and PMOS [4]. Compared with CMOS inverter TIA in [4], the presented TIA employs a current tail to make the g m of M1~M4 refer to the bias current instead of the supply voltage for better supply noise rejection. In order to provide better single-ended to differential conversion for LA input, we include the crosscoupled pair M 7 and M 8 , which act as common-source amplifiers to provide negative voltage gain through the feedback resistor R F . The pseudo-differential configuration of the TIA provides better supply-noise rejection as well as jitter performance than the singled-ended TIA. The simulated gain of TIA is 46dBΩ and the input-referred noise is 2.5μA rms with 20GHz BW. The DC-offset cancellation circuit in Fig. 8.4.2 receives pseudo-differential outputs from the TIA and adjusts the output DC levels for the LA, based on the offset voltage provided by the LPF as shown in Fig. 8.4.1.Circuit schematics of LAs using both conventional and shared-inductor peaking are shown in Fig. 8.4.2. For the LA using conventional inductive peaking, two inductors L 1 are required for each stage. On the other hand, the LA using sharedinductor peaking requires only two inductors L 2 for every two adjacent stages, wherein the inductance value of L 2 is half of L 1 . The reason that L 2 can be only half of L 1 is because by sharing the inductor L 2 between two adjacent stages, the in-phase current...

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IntroductionPixel scaling trend on CMOS image sensor (CIS) calls for a novel technology to improve sensor's optical response being blocked or interfered by metal layers in traditional front-side illumination (FSI) sensor structure. Recently, backside illumination (BSI) sensor technology gradually becomes the main-stream CIS process to achieve virtually 100% fill-factor to boost the optical response and enhance optical angular response due to a shorter optical path. In this paper, a leading-edge N65 0.9μm pixel BSI technology using 300mm bulk silicon wafer is reported with process breakthroughs. Challenges for pixel-size scaling beyond 0.9μm are discussed. Technology OverviewBuilding image sensors with a BSI technology is an effective approach to maintain pixel size scaling trend without sacrificing sensor performance [1][2][3][4]. For pixel sizes less than ~1.75μm, BSI sensor's optical parameters, such as sensitivity, quantum efficiency (QE), optical cross-talk, angular response etc., can be significantly improved over FSI's due to no optical diffraction or blocking effect by routing metal layers along the optical path. Despite of the simple concept to flip the physical sensor with metal structure upside-down, developing the BSI manufacturing process is not a trivial task. Several key process modules that did not exist in traditional IC processes were created and carefully controlled to achieve mass-production capability. The following are the descriptions of the BSI processing and the related module performance.A schematic of BSI process flow is shown in Fig.1. P/P+ epi wafers provide a cost-effective solution compared with SOI wafers. After Back-End-of-Line (BEOL) process is completed, a device wafer runs through a planarization process and is bonded with a carrier wafer. The bonded wafer is then mechanically and chemically thinned down from the bottom side of the device wafer to the target thickness. The new backside Si surface is implanted with a shallow P+ layer followed by laser anneal for dopant activation. Backside antireflection (BARC) layers are coated to further enhance optical sensitivity. Pad opening, color filter array, and packaging process are performed to complete the BSI sensor manufacturing.The aforementioned process utilizes several new tools uncommon to traditional CMOS technology and that poses certain challenges in the process development. The major steps are wafer bonding, thin-down process, and laser anneal. Wafer bonding mainly determines the maximum mechanical stress the BSI wafers can tolerate in following processes including thermal treatment and packaging. It also imposes a certain stress to the bonded device and carrier wafers. Bond voids at the bonding interface and wafer distortion are key parameters of the bonding process. Fig. 2 shows a bonding process window obtained to achieve voidfree and good distortion. Optimized with a bond anneal process, 300mm wafers have been proven to withstand complete BSI process, color filter array (CFA), and packaging.For wafer thin-down process, f...