22FDX TM is the industry's first FDSOI technology double-patterning steps required at the 16/14nm FinFET architected to meet the requirements of emerging mobile, technology nodes. Approximately 75% of the process steps Internet-of-Things (IoT), and RF applications. This platform are common with the 28nm platform enabling high yield achieves the power and performance efficiency of a 16/14nm capability. The gate-first High-K Metal Gate (HKMG) FinFET technology in a cost effective, planar device integration is used to ensure a low cost process flow [3]. A architecture that can be implemented with ~30% fewer typical cross-section of nFET and pFET devices is shown in masks. Performance comes from a second generation FDSOI Fig.1. All active devices are built on SOI whereas passive transistor, which produces nFET (pFET) drive currents of devices and select active devices, such as LDMOS, are 910μA/μm (856μA/μm) at 0.8V and 100nA/μm Ioff. For conventionally formed in the bulk substrate (Fig.2). In ultra-low power applications, it offers low-voltage operation addition to the introduction of FDSOI substrates, new process down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and modules are introduced to support back-bias capability, 0.52V V min for high-density and high-current bitcells, ultra-passive device fabrication, enhanced device performance and low leakage devices approaching 1pA/µm Ioff, and body-technology scale factor (Fig.3). The introduction of a SiGe biasing to actively trade-off power and performance. channel for pFET devices by the condensation technique [4] Superior RF/Analog characteristics to FinFET are achieved and SOI thickness <7nm enable high DC drive currents. A including high f T /f MAX of 375GHz/290GHz and post STI hybrid etch process is used to form back gate 260GHz/250GHz for nFET and pFET, respectively. The contacts and enable the implementation of devices and taphigh f MAX extends the capabilities to 5G and millimeter wave cells in the bulk substrate (Fig.4). Dual in-situ doped epi (>24GHz) RF applications. processes (Si:P and SiGe:B) are formed in combination with a low-k spacer to ensure highly doped source/drain regions I. INTRODUCTION while maintaining low gate-to-drain capacitance (critical for Rising manufacturing costs and emerging applications RF applications). Technology CPP is scaled without adding requiring unparalleled energy efficiency are driving the need extra masking steps relative to the 28nm Front-End-of-Line. for new semiconductor device solutions. For the first time, Dual patterning techniques are used to scale M1/M2 pitch, an increase in the cost per die is observed with the leading to a logic/SRAM die scaling of 0.72x/0.83x relative to introduction of 16/14nm FinFET technologies due to the 28nm Poly/SiON technology node. increased process complexity and mask count. Cost sensitive B. Device Performance IoT and mobile applications are driving new requirements such as increased integration, advanced power management, Device construction utilizes either flip well (SLVT/LV...

In a system consisting of two different lattices, the structural stability is ensured when an epitaxial relationship occurs between them and allows the system to retain the stress, avoiding the formation of a polycristalline film. The phenomenon occurs if the film thickness does not exceed a critical value. Here we show that, in spite of its orthorombic structure, a 14nm-thick NiSi layer can threedimensionally (3D) adapt to the cubic Si lattice by forming transrotational domains. Each domain arises by the continuous bending of the NiSi lattice, maintaining a close relationship with the substrate structure. The presence of transrotational domains does not cause a roughening of the layer but instead it improves the structural and electrical stability of the silicide in comparison with a 24nm-thick layer formed using the same annealing process. These results have relevant implications on thickness scaling of NiSi layers currently used as metallizations of electronic devices.Correspondence should be addressed to : Alessandra Alberti ( Alessandra.Alberti@imm.cnr.it) Acta Crystallographica B, 61, 486-491 (2005) 2

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I. AbstractA high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (V dd =1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 µm 2 . II. Technology DescriptionThe major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated. III. FEOL Performance ResultsA plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-cur...

Embedded-SiGe is shown to be fully compatible with strained-SOI substrates. Despite a lack of lateral lattice mismatch between the SiGe and strained-SOI, the resulting drive current improvement from embedded-SiGe is identical for strained-SOI and standard SOI control (where a lateral lattice mismatch is present). This result isolates the vertical lattice mismatch as the source of stress generation from embedded-SiGe. The concept of a critical length of SiGe beyond the vertical Si-SiGe interface is introduced to explain the observed experimental results, and is confirmed by various SiGe epitaxial fill-height and stress relaxation experiments.

Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12 % and 10 %, respectively, resulting in performance at 1.0 V and 100 nA/µm IOFF of NIDSAT = 1354 µA/µm and PIDSAT = 857 µA/µm. Product-level implementation of asymmetric transistors showed a speed benefit of 12 %, at matched yield and improved reliability.

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