High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

Abstract

I. AbstractA high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 µA/um and 1259 µA/um respectively, at an off-current of 200 nA/um (V dd =1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 µm 2 . II. Technology DescriptionThe major ground rules used in this technology are equivalent to our 65-nm-baseline technology which utilizes DSL for enhanced performance [1]. DSL is a process integration flow that combines tensile and compressive stress silicon nitride liners on nFET and pFET devices respectively, resulting in increased channel strain and performance for both. Fig. 1 shows our baseline flow with additional enhanced strain process steps. Specifically, the embedded SiGe process is implemented with epitaxial SiGe growth in cavities etched into the source/drain areas of the pFETs. The nFETs are covered with a nitride hardmask during recess etch and epitaxial growth of SiGe in the pFET areas. Photolithography is utilized to mask the nFET areas while the hardmask is etched into a spacer in the pFET areas. This spacer defines the proximity of the SiGe to the channel area and prevents SiGe growth on the pFET polysilicon gate electrode. A stress memorization technique (SMT) is implemented for the nFETs where increased tensile strain was achieved by the deposition of a stress dielectric film and subsequent thermal anneal.The remaining process flow steps are equivalent to our baseline CMOS process, except for a modified Ni silicide process that achieves improved contact and stability on SiGe. This is followed by DSL implementation in the middle-of-line (MOL) [2]. A cross-sectional TEM image of a completed device is shown in Fig. 2, also shown is an AFM image of the surface morphology of the source/drain area of the pFET demonstrating a smooth RMS roughness value of 0.11 nm. The advanced-low-K dielectric film used in the BEOL interconnect levels is based on the K=2.75 material previously discussed [3]. This film has been optimized for lower permittivity (K=2.75) and stress. Extendibility of the film into both 2x and 4x fatwire levels has been demonstrated. III. FEOL Performance ResultsA plot of the Ion-Ioff characteristics is shown in Fig. 3 along with the transistor characteristics in Fig. 4 at 1.0 V Vdd, where the threshold voltage roll-off is well-behaved down to 30 nm gate length, and sub-threshold swing is maintained at ~110 mV/dec (Fig. 5-6). pFET AC switching on-current of 735 µA/µm at off-current of 200 nA/µm with a corresponding DC on-current of 700 µA/µm was achieved. For the nFET, the AC switching on-current was 1259 µA/µm and the DC on-cur...

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“…A process step that is particularly sensitive to surface contamination and thus to condensation defects is epitaxial growth of SiGe, used for strain engineering of pFET devices (embedded SiGe or eSiGe) [6], [7]. In particular when removing oxide from the silicon surface we have to take care not to deposit any contaminants before the wafers enter the epitaxy tool [8].…”

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

“…This compressive SiN is then patterned and removed from the nMOS region before finishing off the DSL process. The final device structure features a tensile stress liner on nMOS and a compressive stress liner on pMOS on the same wafer as shown in Figure 6 from IBM's 65-nm CMOS technology [31]. DSL was demonstrated to improve nMOS and pMOS drive currents by 11% and 20%, respectively, for a sub 45-nm gate length CMOS [30].…”

From Strain to High-K/Metal Gate ¿ the 65 ¿ 45 nm Transition

“…4(b) shows the overlap of the two layers. In addition, AMD claims 2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference the use of memorized stress [7] for the N-FETs.…”