Effectiveness of Embedded-SiGe in Strained-SOI Substrates and Implications on Embedded-SiGe Stress Transfer Mechanics

Abstract

Embedded-SiGe is shown to be fully compatible with strained-SOI substrates. Despite a lack of lateral lattice mismatch between the SiGe and strained-SOI, the resulting drive current improvement from embedded-SiGe is identical for strained-SOI and standard SOI control (where a lateral lattice mismatch is present). This result isolates the vertical lattice mismatch as the source of stress generation from embedded-SiGe. The concept of a critical length of SiGe beyond the vertical Si-SiGe interface is introduced to explain the observed experimental results, and is confirmed by various SiGe epitaxial fill-height and stress relaxation experiments.

Integration Challenges for Advanced Process-Strained CMOS on Biaxial-Strained-SOI (SSOI) Substrates

“…That the embedded-SiGe works equally well, if not better on SSOI, indicates that it is the vertical lattice mismatch between Si-SiGe which is responsible for embedded-SiGe stress benefits in PMOS. This has been further detailed in [12].…”

Strained Silicon on Wafer Level by Waferbonding: Materials Processing, Strain Measurements and Strain Relaxation

“…Here, an I DAST improvement of only 10 -20% was obtained up to now (17). The main reason was the interaction with process-induced stressors reducing the effect of the biaxial strain (18). This means that applications of SSOI wafers require modifications of existing CMOS processes.…”

Stress Manipulation with Strained-Silicon Directly (SSOI) on Insulator

“…10). Furthermore, by careful strain engineering conventional uniaxial stressors like embedded SiGe S/D and stressed nitride liners are fully compatible with SSOI [1], leading to a mixed-strain approach. Together with other techniques like Ge-condensation, this hybrid-strain approach may be applied to new transistor architectures like FinFETs, UT-SOI, and SGOI [2,3].…”