Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

Horstmann, Μ.; Wei, A.; Kammler, Thorsten; Höntschel, J.; Bierstedt, H.; Feudel, T.; Frohberg, K.; Gerhardt, Matthias; Hellmich, A.; Hempel, Klaus; Hohage, J.; Javorka, P.; Klais, J.; Koerner, G.; Lenski, M.; Neu, Andreas; Otterbach, R.; Press, P.; Reichel, Carsten; Trentsch, M.; Trui, Bernhard; Salz, H.; Schaller, Μ.; Engelmann, H.; Herzog, O.; Ruelke, H.; Hubler, P.; Stephan, R.; Greenlaw, D.; Raab, M.; Kepler, N.; Chen, H.; Chidambarrao, D.; Fried, D.; Holt, J.; Lee, W.; Nii, H.; Panda, Soumya Ranjan; Satô, Takahiro; Waite, Andrew; Shen, Liming; Rim, K.; Schepis, D.; Khare, Mukesh; Huang, Shu-Hao; Pellerin, John; Su, Li

doi:10.1109/iedm.2005.1609315

Cited by 49 publications

(21 citation statements)

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“…Additional uniaxial stress is often introduced by growing compressive or tensile capping layers [27][28][29]. The advantage of local stress techniques is that they can be combined [30] and superimposed [31] on the same wafer.…”

Section: Strain Engineering Techniquesmentioning

confidence: 99%

Modeling of modern MOSFETs with strain

et al. 2009

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We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22 nm technology node and beyond.Keywords MOSFETs modeling · Shear strain · Two-band k·p model for conduction band · Valley splitting · Mobility and current enhancement

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Section: Strain Engineering Techniquesmentioning

confidence: 99%

Modeling of modern MOSFETs with strain

et al. 2009

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“…Basically, each of these techniques is intended to intentionally apply a uniaxial stress in the channel region to improve its transport properties. Horstmann et al [4], demonstrated how these techniques add. On NMOS, tensile stress liner and stress memory effect can together induce as much as 53% Ion enhancement, while, on PMOS compressive stress liner and eSiGe S/D induce 32% Ion enhancement.…”

Section: Introductionmentioning

confidence: 96%

“…TEM cross section of NMOS with stress memory and tensile stress liner on SOI (left), PMOS with embedded SiGe and compressive stress liner on SOI[4] …”

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confidence: 99%

Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

2006

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In this paper we highlight the complementarities of process-induced stress and wafer level stress (sSOI). We first present a state of the art of the various strain engineering techniques used in production for both PMOS and NMOS devices and discuss their scalability for 45nm and 32 nm nodes using some mechanical modeling. In a second part, we explain how wafer level stress can be used together with processinduced stress to overcome these difficulties and insure further performance enhancement. We discuss some device data showing compatibility and additivity of process-induced and wafer level stress. Finally, we give an overview of further sSOI developments that will insure scalability beyond 32nm.

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“…The stressors have been introduced intentionally and integrated in the manufacturing processes to improve device performance [3]. The improvement in PMOS drive current is obtained by use of compressive plasma-enhanced nitride (CPEN) film and embedded-SiGe (e-SiGe), which improve the hole mobility by the creation of a compressive stress in the channel [4,5].…”

Section: Introductionmentioning

confidence: 99%

“…The electron mobility and the corresponding NMOS drive current improvement is achieved by use of tensile plasma-enhanced nitride (TPEN) film on top of the device as well as stress memorization techniques [4][5][6]. The stress techniques are shown to be additive and have been applied to both bulk and SOI technologies [3][4][5][6]. In addition, the shallow trench isolation (STI) also exerts compressive stress, which has been studied in more detail compared to the other intentional stressors.…”

Section: Introductionmentioning

confidence: 99%

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

Sultan

Faricelli

Suryagandh

et al. 2009

2009 10th International Symposium on Quality Electronic Design

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Stressors have been used since 90 nm technology to improve device performance to overcome the limitations of scaling. The stressors, including, -CPEN, TPEN, SMT, and e-SiGe to improve NMOS and PMOS drive current exhibit proximity dependence. In addition, unintentional stressors such as STI edge proximity introduce additional layout dependencies. Two devices with the same L and W can have significantly different drive strength depending on their surroundings. There have been limited studies to optimize the design layout to reduce the layout-dependent stress degradation. Circuit and layout designers have few tools they can use to quickly and effectively optimize the layout to reduce device degradation due to layoutdependent stress effects. In this paper, we present a comprehensive set of CAD utilities, and stress-related layout guidelines to optimize the layout for full custom macros to reduce the layout-dependent stress effects prior to doing full timing characterization, including stress effects.

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Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

Cited by 49 publications

References 0 publications

Modeling of modern MOSFETs with strain

Modeling of modern MOSFETs with strain

Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design

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