Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

Cayrefourcq, I.; Boussagol, Alice; Celler, G. K.

doi:10.1149/1.2355837

Cited by 15 publications

(12 citation statements)

References 15 publications

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“…Following successful bonding of both wafers, the donor wafer was split off with the ion cut exfoliation technique. The surface is then finished with an etching process to completely remove all traces of the Si 1-x Ge x film, resulting in a Ge-free bi-axially strained Si film on amorphous SiO 2 insulator [4,5]. The insulating buried oxide beneath the SOI film is on the order of 145 nm thick.…”

Section: Sample Fabricationmentioning

confidence: 99%

Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting

Mamun¹,

Zhang²,

Baumgart³

et al. 2014

ECS Trans.

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Biaxial tensile strained Si layers grown epitaxially on SiGe have attracted renewed attention for high performance CMOS devices. Strain engineering for mobility enhancement is an attractive option to improve CMOS device performance. Epitaxial Si1-xGex and most recently Ge-free bi-axially strained sSOI are among the serious candidates for higher mobility channel material. We demonstrate how the fabrication of thin single crystal Si devices by wafer bonding and hydrogen ion cut film exfoliation technique is affecting their nanomechanical properties compared to bulk single crystal Si. Although both the handle wafer and the bonded thin device layer are single crystal Si, it turns out that their nanomechanical properties differ considerably. Using nanoindentation, we measured the properties of SOI and bi-axially tensile strained sSOI and benchmarked the results against single crystal bulk Si. The experimental results indicate that the hardness of the strained thin Si films varies significantly.

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Section: Sample Fabricationmentioning

confidence: 99%

Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting

Mamun¹,

Zhang²,

Baumgart³

et al. 2014

ECS Trans.

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“…Other less destructive techniques, such as Raman or X-Ray Diffraction, are essential to determine lattice disorder, strain profile or even Ge composition in Ge-containing substrates (16)(17).…”

Section: Off-line Monitoring Techniquesmentioning

confidence: 99%

“…As far as crystalline quality analysis of silicon (and Ge-based semiconductor oninsulator substrates) is concerned, preferential etching techniques (15), that we will detail below, are mandatory for a fast and efficient monitoring of structural quality. Other less destructive techniques, such as Raman or X-Ray Diffraction, are essential to determine lattice disorder, strain profile or even Ge composition in Ge-containing substrates (16)(17).…”

Section: Off-line Monitoring Techniquesmentioning

confidence: 99%

SOI and Other Semiconductor-On-Insulator Substrates Characterization

et al. 2009

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We focus in this paper on SOI and new engineered on-insulator substrates characterization. After a short review of on-line characterization techniques, we will detail off-line monitoring techniques such as preferential etching and Raman spectroscopy. We will especially highlight their complementarities on strained layers and the need for a proper evaluation of structural quality of on-insulator substrates.

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“…Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes which can be further amplified by combining them with a strained silicon substrate (sSOI) [8,9]. The alternative and probably complementary approach is the dual crystal orientation surface with (100) and (110) Si surfaces for the n and p-channels, respectively [7,10].…”

Section: High Performance Substratesmentioning

confidence: 99%

Embedding Device Solutions in Engineered Substrates

Mazuré¹

2007

ECS Trans.

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A review of the advances in Smart Cut engineered substrates and the impact on device architecture and IC design is given. Primarily focusing on CMOS applications, mobility enhancing substrates, fully depleted device compatibility to SOI product capability and multi-gate FinFETs will be reviewed. IntroductionA simple structure like silicon on insulator (SOI) has allowed the IC industry to optimize the MOSFET architecture by reducing parasitic capacitances to the substrate, cutting device leakage, improving device speed while reducing power consumption, decreasing considerably soft error rate, and so forth. The benefits and potential of SOI have been known since the 60's [1]. The real issue for an industrial SOI development was SOI substrate availability and wafer quality. This roadblock vanished with the invention of Smart Cut TM [2,3], a single crystal thin layer transfer technology. The simplicity of this technique underlines simultaneously the power and potential of Smart Cut technology and explains why it has become today the industrial standard for thin layer transfer [4].Smart Cut technology consists in defining a splitting region within the donor substrate by ion implantation (e.g. H), which allows a thin film to transfer to a handle wafer after bonding and splitting. The thickness removed from the donor wafer is negligible compared to the total wafer thickness. Consequently, the donor wafer can be reused many times. A range of 10 nm up to a few 10 3 nm in top Si and buried oxide (BOX) thickness is easily covered by this technology.Beyond SOI, Smart Cut technology opens the door to substrate engineering, i.e. the capability to design new substrates tailored to specific applications [5]. It is possible to amplify certain device properties while weakening others by combining different materials or crystal orientations, adding strained layers, or simply creating a new composite substrate.High performance ICs continue to be the driver for a specialized family of advanced substrates. Ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques [6], as well as improved thermal dissipation to reduce the impact of hot spots on MOSFET performance are among the most obvious engineered substrate solutions [5]. Direct silicon Bonding (DSB) adds a high-end mobility enhancing substrate to the bulk Si IC architectures [7]. Non-planar device architectures like FinFETs take advantage of the buried oxide or nitride as an etch stop for fin height definition, thus reducing fin variability [5].A review of the advances in Smart Cut engineered substrates and the impact on device performance and IC design is given below. High Performance SubstratesBeyond the 90nm technology node, the electron and hole mobility enhancement have become essential to assure device performance increase while scaling. Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes whi...

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Wafer-Level Stress in Combination with Process Induced Stress for Optimum Performance Enhancement

Cited by 15 publications

References 15 publications

Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting

Nanomechanical Properties of Standard and Strained SOI Films Fabricated by Wafer Bonding and Layer Splitting

SOI and Other Semiconductor-On-Insulator Substrates Characterization

Embedding Device Solutions in Engineered Substrates

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