In order to continue improving strained silicon-on-insulator ͑sSOI͒ crystal quality, high-resolution defect monitoring needs to be developed and implemented for further defects reduction. The study presented in this paper evaluates and compares two techniques for revealing crystal defects in sSOI wafers produced by the Smart-Cut Technology. Two different etching techniques, based on the use of gaseous HCl in an epitaxy reactor or of a diluted Secco wet etching solution, were compared on their ability to delineate various defects. Both techniques should provide the required defects density resolution for analysis of thin and thick strained silicon layers. For the sake of analysis and discussion, samples with a high defects density were chosen in order to simplify the quantitative comparison ͑within the resolution of optical microscopy͒. We have observed a difference in etching selectivity between the two techniques. After a statistical comparison of defects delineated by the two techniques ͑in terms of threading dislocations, areal densities, and planar defect linear densities͒, we have demonstrated complementarities rather than a direct correlation between the HCl and Secco etch. The HCl etch seems quite suitable for revealing threading dislocations through etch pits and shows a higher sensitivity for pit delineation compared to Secco ͑difference corresponding to a factor of 10 in defects density͒. Meanwhile, the Secco chemical etching appears more appropriate to highlight the planar defects ͑linear density between 600 and 1000 cm −1 ͒. Moreover, a minimum etched thickness for sSOI defect revelation has been determined for both techniques ͑between 26 and 36 nm for HCl and between 20 and 30 nm for Secco for a 600 Å thick starting layer͒. Because the Secco etch is particularly sensitive for the delineation of various types of defects ͑isolated etch pits and planar defects͒, it is now used by us as a quality control method for SOI and sSOI. Thanks to it sSOI process improvements are tracked and current and next generations of this product evaluated.
Bi-axially highly-strained Silicon-On-Insulator (sSOI) substrates with a tensile stress up to 2.5 GPa have been obtained by Smart CutTM technology. Thin strained silicon (sSi) layers epitaxially grown on relaxed Si0.6Ge0.4 virtual substrates (VS) were used as starting materials. The threading dislocation density in those sSi layers was in the low 105 cm-2. Some stacking faults were also present in those highly strained Si films. The evolution of this linear defect density was characterized as a function of the sSi thickness by Secco etch. 2.5 GPa sSOI wafers have been demonstrated in 200 mm diameter. Stress uniformity σ equal to 1.14% and 2 nm thickness range has been obtained for 8 nm thick sSi layers.
Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) devices and FinFETs, respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances state that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10nm node. Innovations will be necessary for lower, more advanced node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication. This paper reports our latest achievements in SOI-type bonded substrates for advanced technology nodes.
Introduction of hybrid orientation substrates has led to the development of CMOS technologies in which NMOS transistors are fabricated on (100) Si and PMOS on (110) Si. This maximizes the crystal orientation dependent mobilities of electrons and holes. The Smart Cut technology has been successfully applied to fabricate hybrid orientation substrates with a buried oxide between the top Si layer and the bulk substrate having two different crystal orientations. This paper describes the application of the Smart Cut method for the fabrication of the directly (i.e. with no oxide in between) bonded 300 mm Si engineered substrates. The technological challenges, process flow and the results of the wafer characterization are presented and discussed.
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