Highly-Strained Silicon-On-Insulator Development

Akatsu, T.; Hartmann, Jean‐Michel; Aulnette, C.; Vaillant, Yves-Matthieu Le; Rouchon, D.; Abbadie, A.; Bogumilowicz, Y.; Portigliatti, L.; Colnat, Cyrille; Boudou, Nicolas; Lallement, F.; Triolet, Fanny; Figuet, C.; Martinez, Muriel; Nguyen, P.; Delattre, Cécile; Tsyganenko, Kira; Berne, Cécile; Allibert, F.; Deguet, C.

doi:10.1149/1.2357060

Cited by 19 publications

(13 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The engineered substrates ͓SOI, sSOI, and extra-strained Si ͑xsSOI͔͒ listed in Table I were prepared by Smart Cut technology. 11 Strained Si and xsSOI were initially grown epitaxially on Si 0.8 Ge 0.2 and Si 0.7 Ge 0.3 , respectively. The thickness of the top Si layers was measured by spectroscopic ellipsometer ͑Woollam, VASE͒ as listed in Table I; the film thickness values were also crosschecked using high-resolution transmission electron microscopy ͑HRTEM, JEOL 2010F͒.…”

Section: Methodsmentioning

confidence: 99%

Experimental Study of ALD HfO[sub 2] Deposited on Strained Silicon-on-Insulator and Standard SOI

Tapily

Shrestha

et al. 2008

J. Electrochem. Soc.

View full text Add to dashboard Cite

HfO 2 films of 4 nm were deposited by atomic layer deposition on silicon-on-insulator ͑SOI͒ substrates with various amounts of intentionally introduced lattice strain and several film thicknesses. After postdeposition annealing ͑PDA͒, the samples were studied by Rutherford backscattering spectroscopy, Raman spectroscopy, high-resolution transmission electron microscopy ͑HRTEM͒, electron energy-loss spectroscopy ͑EELS͒, and X-ray photoelectron spectroscopy ͑XPS͒. The as-deposited HfO 2 film showed a good stoichiometry and thickness uniformity. The strain in strained SOI ͑sSOI͒ layers remained after high-temperature PDA at 1100°C. HRTEM images showed that, while HfO 2 films on standard nonstrained SOI became polycrystalline after PDA at 600°C, HfO 2 films on sSOI remained amorphous. The strain in the sSOI layer also suppressed the interlayer ͑IL͒ growth during PDA. The EELS and XPS results confirmed the interdiffusion across the HfO 2 /Si interface. The XPS data also showed that the formation of Hf-O-Si bonds depends on the SOI lattice strain and thickness. The SOI thickness is critical to reduce the formation of silicate in the IL.Hafnium-based high-K dielectrics have been extensively studied as a replacement for Si dioxide or Si oxynitride ͑SiO x N y ͒-based gate dielectrics in future generation complementary metal-oxide semiconductor devices. 1,2 However, an unstable interface with Si limits the equivalent oxide thickness scalability, and the accumulation of high fixed charge degrades the carrier mobility of high-K dielectrics. 3 Silicon-on-insulator ͑SOI͒ wafer technology reduces parasitic effects and requires less current for switching. 4 Substrates with a higher mobility, such as strained Si and Ge, help to compensate for the reduced mobility of a high-K gate stack. 5,6 Combining SOI with strained Si technology into strained SOI ͑sSOI͒ significantly increases the device speed and reduces power consumption. 7,8 It has been reported that the strained Si is stable up to an annealing temperature of 1000°C for 30 s. 9,10 Until now, the effect of strained Si in sSOI on HfO 2 /Si interlayer growth and HfO 2 quality has remained unclear. In this paper, we deposited 4 nm HfO 2 film by atomic layer deposition ͑ALD͒ on SOI and sSOI substrates with a different amount of strain and various thicknesses. The effect of high-temperature annealing on strain relaxation was studied and the effects of the strained Si layer thickness and the amount of strain on the interlayer ͑IL͒ properties were then evaluated. ExperimentalSilicon substrates were cleaned by dipping in 2% HF for 4 min followed by a deionized water rinse to remove native oxide, and were immediately transferred to the ALD reactor chamber for HfO 2 deposition. The engineered substrates ͓SOI, sSOI, and extra-strained Si ͑xsSOI͔͒ listed in Table I were prepared by Smart Cut technology. 11 Strained Si and xsSOI were initially grown epitaxially on Si 0.8 Ge 0.2 and Si 0.7 Ge 0.3 , respectively. The thickness of the top Si layers was measured by spectroscopic ellipsometer...

show abstract

Section: Methodsmentioning

confidence: 99%

Experimental Study of ALD HfO[sub 2] Deposited on Strained Silicon-on-Insulator and Standard SOI

Tapily

Shrestha

et al. 2008

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…Recent results also show that 2.5GPa strained Si sSOI can be manufactured [18] opening further the process window for sSOI based stressors. Figure 4.…”

Section: Strained Silicon On Insulatormentioning

confidence: 96%

Embedding Device Solutions in Engineered Substrates

Mazuré¹

2007

ECS Trans.

View full text Add to dashboard Cite

A review of the advances in Smart Cut engineered substrates and the impact on device architecture and IC design is given. Primarily focusing on CMOS applications, mobility enhancing substrates, fully depleted device compatibility to SOI product capability and multi-gate FinFETs will be reviewed. IntroductionA simple structure like silicon on insulator (SOI) has allowed the IC industry to optimize the MOSFET architecture by reducing parasitic capacitances to the substrate, cutting device leakage, improving device speed while reducing power consumption, decreasing considerably soft error rate, and so forth. The benefits and potential of SOI have been known since the 60's [1]. The real issue for an industrial SOI development was SOI substrate availability and wafer quality. This roadblock vanished with the invention of Smart Cut TM [2,3], a single crystal thin layer transfer technology. The simplicity of this technique underlines simultaneously the power and potential of Smart Cut technology and explains why it has become today the industrial standard for thin layer transfer [4].Smart Cut technology consists in defining a splitting region within the donor substrate by ion implantation (e.g. H), which allows a thin film to transfer to a handle wafer after bonding and splitting. The thickness removed from the donor wafer is negligible compared to the total wafer thickness. Consequently, the donor wafer can be reused many times. A range of 10 nm up to a few 10 3 nm in top Si and buried oxide (BOX) thickness is easily covered by this technology.Beyond SOI, Smart Cut technology opens the door to substrate engineering, i.e. the capability to design new substrates tailored to specific applications [5]. It is possible to amplify certain device properties while weakening others by combining different materials or crystal orientations, adding strained layers, or simply creating a new composite substrate.High performance ICs continue to be the driver for a specialized family of advanced substrates. Ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques [6], as well as improved thermal dissipation to reduce the impact of hot spots on MOSFET performance are among the most obvious engineered substrate solutions [5]. Direct silicon Bonding (DSB) adds a high-end mobility enhancing substrate to the bulk Si IC architectures [7]. Non-planar device architectures like FinFETs take advantage of the buried oxide or nitride as an etch stop for fin height definition, thus reducing fin variability [5].A review of the advances in Smart Cut engineered substrates and the impact on device performance and IC design is given below. High Performance SubstratesBeyond the 90nm technology node, the electron and hole mobility enhancement have become essential to assure device performance increase while scaling. Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes whi...

show abstract

“…The low intensity of the peaks coming from the SiGe transition mode do not facilitate either the quantitative analysis. Before annealing Figure 6 represents a typical Raman spectrum of a dual channel sSi cap / c-SiGe stack, grown on a eXtra Strained Silicon-On-Insulator (XsSOI) substrate (39) …”

Section: Hcl Hcl Hclmentioning

confidence: 99%

SOI and Other Semiconductor-On-Insulator Substrates Characterization

et al. 2009

Self Cite

View full text Add to dashboard Cite

We focus in this paper on SOI and new engineered on-insulator substrates characterization. After a short review of on-line characterization techniques, we will detail off-line monitoring techniques such as preferential etching and Raman spectroscopy. We will especially highlight their complementarities on strained layers and the need for a proper evaluation of structural quality of on-insulator substrates.

show abstract

Highly-Strained Silicon-On-Insulator Development

Cited by 19 publications

References 4 publications

Experimental Study of ALD HfO[sub 2] Deposited on Strained Silicon-on-Insulator and Standard SOI

Experimental Study of ALD HfO[sub 2] Deposited on Strained Silicon-on-Insulator and Standard SOI

Embedding Device Solutions in Engineered Substrates

SOI and Other Semiconductor-On-Insulator Substrates Characterization

Contact Info

Product

Resources

About