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Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (>10 nm) seems to be a promising way for p-type memory applications.

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We present a detailed study of the growth of Ge nanocrystals (NCs) on SiO2 by chemical vapor deposition. A two-step process was developed. First, Si nuclei are deposited on SiO2 using SiH4 as a gaseous precursor. Then, Ge NCs grow selectively on the Si nuclei previously formed. The density of the Ge NCs is adjustable in between 109 and 1012 cm−2. Their mean size varies between 5 and 50 nm. We have shown, combining grazing incidence x-ray diffraction and x-ray photoelectron spectroscopy, that pure Ge NCs are grown in a polycrystalline phase on a SiO2 surface.

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We have studied the influence of SiO 2 surface properties on the nucleation and growth of silicon quantum dots ͑Si-QDs͒ deposited by SiH 4 low-pressure chemical vapor deposition ͑LPCVD͒. First, the effect of siloxane groups ͑Si-O-Si͒ strain at the SiO 2 surface layer, characterized by Fourier transform infrared ͑FTIR͒ spectroscopy, is studied. We evidenced an increase of Si-QD nucleation with the strain of siloxane groups in the SiO 2 substrate layer. Second, the Si-QD nucleation strongly depends on the surface silanol group ͑Si-OH͒ density. This density, controlled by chemical and thermal treatments, is measured by multiple internal reflexion ͑MIR͒ FTIR. Very high Si-QD densities larger than 10 12 /cm 2 are obtained on highly hydroxylated SiO 2 .During the last few years, silicon quantum dots ͑Si-QDs͒ have been studied for nanoelectronics applications. Their unique physical properties, size confinement effect, and coulomb blockade phenomena make Si-QDs suitable for use in new silicon-based devices like single electron transistors 1 or quantum dot floating gate memories. 2 For room-temperature operation of such devices, nanometric size silicon dots ͑Ͻ10 nm͒ are required.Low-pressure chemical vapor deposition ͑LPCVD͒ is a good way to obtain Si-QDs for industrial applications because of its metal-oxide field effect transistor ͑MOSFET͒ technology compatibility. By controlling the early stages of the Si film growth, silicon crystallites of nanometer size ͑5 nm͒ are obtained. 3 It has been shown that Si-QDs elaborated by SiH 4 LPCVD could exhibit coulomb blockade at room temperature 4 but to successfully integrate Si-QDs in devices their alignment must be controlled. Results were recently obtained by Baron et al. 5 who deposited an ordered array of Si-QDs by SiH 4 LPCVD on a substrate realized by wafer bonding with a periodic strain field at the surface.In order to obtain operating devices, size, size uniformity, and Si-QDs density must also be controlled with great precision and reproducibility. For floating gate memory applications, densities between 10 11 and 10 12 /cm 2 are required. To fabricate a single electron transistor with a lateral current transport, the spacing between dots should be lower than 2 nm. Typically, for a dot size of 5 nm, these conditions lead to a density of 3 ϫ 10 12 Si-QDs/cm 2 . 6 Si-QD size and density are piloted by pressure and temperature conditions. The chemical nature of the substrates 3 and its physical properties such as stress, roughness, or defects can play an important role in silicon nucleation. Voutsas and Hatalis 7 showed that the chemical properties of the SiO 2 surface also strongly affect the first stages of silicon deposition.In this paper, we separately investigated the influence of ͑i͒ the strain of siloxane ͑Si-O-Si͒ groups and ͑ii͒ the surface silanol ͑Si-OH͒ density on thermally grown SiO 2 layers on Si-QD nucleation by SiH 4 LPCVD. These characteristics are controlled by the oxidation process and postoxidation chemical and thermal treatments, respectively. Experim...

An atomic force microscopy (AFM) tip has been used to manipulate silicon nanocrystals deposited by low-pressure chemical vapour deposition on thermally oxidized p-type Si wafer. Three nanomanipulation methods are presented. The first one catches a nanocrystal with the AFM tip and deposits it elsewhere: the tip is used as an electrostatic ‘nano-crane’. The second one simultaneously manipulates a set of nanocrystals in order to draw well-defined unidimensional lines: the tip is used as a ‘nano-broom’. The third one manipulates individual nanocrystals with a precision of about 10 nm using both oscillating and contact AFM modes. Switching from strong interaction forces (chemical) to weak ones (van der Waals, electrostatic or capillarity) is the basis of these manipulation methods. We have applied the second method to connect two electrodes drawn by e-beam and lift-off with a 70 nm long silicon nanocrystal chain. Current versus voltage characterization of the nanofabricated device shows that the increase in nanocrystal density gives rise to conduction between the connected electrodes. Resonant tunnelling effects resulting from Si nanocrystal (nc-Si) multiple tunnel junctions have been observed at 300 K. We also show that offset charges directly influence the position of the resonant tunnelling peaks. Finally, the possibility of manipulating nc-Si with a diameter of around 5 nm is shown to be a promising way to fabricate single electron devices operating at room temperature and fully compatible with silicon technology.

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