Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

Hoentschel, J.; Wei, A.; Wiatr, Maciej; Gehring, A. U.; Scheiper, Th.; Mulfinger, Robert; Feudel, Thomas; Lingner, T.; Poock, Andre; Muehle, S.; Krueger, C.; Herrmann, T.; Klix, W.; Stenzel, R.; Stephan, R.; Huebler, P.; Kammler, Thorsten; Shi, P.; Raab, M.; Greenlaw, D.; Horstmann, Μ.

doi:10.1109/iedm.2008.4796775

Cited by 9 publications

(11 citation statements)

References 2 publications

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“…In order to estimate the combined effect for the proposed approaches, both methods are also intensively simulated. Only half of the channels are To determine the advantages of the LAC and inLAC devices, 42,43) the simulated I D -V G characteristics of the nominal control, DMG, DMG + LAC, and DMG + inLAC devices are examined, as shown in Fig. 10.…”

Section: Resultsmentioning

confidence: 99%

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Lee

Yiu

et al. 2011

Jpn. J. Appl. Phys.

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In this work, we explore for the first time dual-material gate (DMG) and inverse DMG devices for suppressing the random-dopant (RD)-induced characteristic fluctuation in 16 nm metal-oxide-semiconductor field-effect-transistor (MOSFET) devices. The physical mechanism of suppressing the characteristic fluctuation of DMG devices is observed and discussed. The achieved improvement in suppressing the RD-induced threshold voltage, on-state current, and off-state current fluctuations are 28, 12.3, and 59%, respectively. To further suppress the fluctuations, an approach that combines the DMG method and channel-doping-profile engineering is also advanced and explored. The results of our study show that among the suppression techniques, the use of the DMG device with an inverse lateral asymmetric channel-doping-profile has good immunity to fluctuation. #

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Section: Resultsmentioning

confidence: 99%

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Lee

Yiu

et al. 2011

Jpn. J. Appl. Phys.

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“…However, the is often lowered by the short channel effects (SCEs), which become more severe with continuing gate scaling for higher speed. Although an asymmetric gate [1]- [3] structure can alleviate some SCEs, the required angle-implants need separate masks and additional fabrication steps to a standard CMOS process. Furthermore, the emphasis has been on improving parameters that are important mostly for digital circuits, such as off-state leakage current, threshold voltage roll-off, and sub-threshold swing (SS).…”

Section: Introductionmentioning

confidence: 99%

Improvement of SOI MOSFET RF Performance by Implant Optimization

Chen

Knecht

Kedzierski

et al. 2010

IEEE Microw. Wireless Compon. Lett.

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The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the f max of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer. Index Terms-Fully depleted silicon on insulator (FDSOI), mixed-signal CMOS, RF MOSFET, silicon on insulator (SOI).

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“…The generated holes are swept into the substrate, thus giving rise to substrate leakage current and enhanced impact ionization due to the forward biasing of the source/substrate junction. [11][12][13][14] Asymmetric doped channel MOSFETs have recently been investigated by several authors in bulk 15,16) and SOI technologies [2][3][4][17][18][19] as a possible solution for the problems of premature hot-carrier effects and threshold voltage roll-off issues in deep sub-micron devices. Generally, the doping of the channel region is performed by a tilted ion implantation in the source side after the gate formation.…”

Section: Introductionmentioning

confidence: 99%

“…Generally, the doping of the channel region is performed by a tilted ion implantation in the source side after the gate formation. [18][19][20][21] The high concentration at the source end improves the threshold voltage roll-off and drain induced barrier lowering, while the low doping near the drain ensures high mobility, reduced peak electric field and impact ionization.…”

Section: Introductionmentioning

confidence: 99%

“…Hot electron degradation, punch-through suppression, and threshold variations with channel length are some of the important issues that can be addressed with proper channel doping profile design. [11][12][13][14][15][16][17][18][19][20][21][22] In recent years, in the stage of the sub-micron and deep sub-micron MOSFETs, halo implantation profiles, like symmetric and asymmetric halo MOSFETs, are the most reasonable technique that have been investigated in this respect by various researchers. [17][18][19][20][21][22] Utilization and optimization of all profiles of halo implantation for the fully-depleted SOI (FD-SOI) MOSFETs are reported on many papers.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices

Elahipanah¹,

Orouji²

2009

Jpn. J. Appl. Phys.

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For first time, we report a novel deep sub-micron fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor (FD SOI MOSFET) where the channel layer consists of two sections with a step doping (SD) region in order to increase performance and reliability of the device. This new structure that called SD FD SOI structure (SDFD-SOI MOSFET), were used for reaching suitable threshold voltage upon device scaling and reliability improvement. We demonstrate that the electric field was modified in the channel and common peak near the source junction have been reduced in the SDFD-SOI structure. The device demonstrates large enhancements in performance areas such as current drive capability, output resistance, hot-carrier reliability and threshold voltage roll-off. It was found that the device performance is very much dependent upon the SD region parameters. Simulation results show that the proposed structure improved on/off current ratio, and saturated output characteristics compared with conventional SOI structure (C-SOI MOSFET). Also, it was shown that substrate current of SDFD-SOI MOSFET is much lower than the C-SOI MOSFET which presented the lower hot-carrier degradation in proposed MOSFET. Results show that the most short-channel problems in very large scale integrated circuits (VLSI) could be solved and the proposed SDFD-SOI MOSFETs can work very well in deep sub-micron and nanoscale regime.

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Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

Cited by 9 publications

References 2 publications

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

Improvement of SOI MOSFET RF Performance by Implant Optimization

A Novel Step-Doping Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor for Reliable Deep Sub-micron Devices

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