By developing a two-dimensional (2D) full quantum simulation, the attributes of carbon nanotube field-effect transistors (CNTFETs) in different temperatures have been comprehensively investigated. Simulations have been performed by employing the self-consistent solution of 2D Poisson-Schrödinger equations within the nonequilibrium Green's function (NEGF) formalism. Principal characteristics of CNTFETs such as current capability, drain conductance, transconductance, and subthreshold swing (SS) have been investigated. Simulation results present that as temperature raises from 250 to 500 K, the drain conductance and on-current of the CNTFET improved; meanwhile the on-/off-current ratio deteriorated due to faster growth in off-current. Also the effects of temperature on short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off have been studied. Results show that the subthreshold swing and DIBL parameters are almost linearly correlated, so the degradation of these parameters has the same origin and can be perfectly influenced by the temperature.
PostprintThis is the accepted version of a paper published in IEEE Electron Device Letters. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination.Citation for the original published paper (version of record):Elahipanah, H., Salemi, A., Zetterling, C-M., Östling, M. (2015) 5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension.
IEEE Electron Device Letters
IndexTerms-4H-SiC, multiple-shallow-trench JTE, implantation-free, high-voltage BJT.
A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10 −6 · cm 2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.
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