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PostprintThis is the accepted version of a paper published in IEEE Electron Device Letters. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination.Citation for the original published paper (version of record):Elahipanah, H., Salemi, A., Zetterling, C-M., Östling, M. (2015) 5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension. IEEE Electron Device Letters IndexTerms-4H-SiC, multiple-shallow-trench JTE, implantation-free, high-voltage BJT.

A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10 −6 · cm 2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

Low temperature epitaxy (LTE) in Chemical Vapor Deposition (CVD) refers to 350-650 • C interval. This temperature range is critical for this process since the thermal and lattice mismatch (or strain relaxation) issues diminish in advanced BiCMOS processing. The modeling of the epitaxy process is a vital task to increase the understanding the growth process and to design any desired device structure. In this study, an empirical model for Si 2 H 6 /Ge 2 H 6 -based LTE of SiGe is developed and compared with experimental work. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperatures. A good agreement between the model and the experimental data is obtained.

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxidesemiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters (γ) are observed at oxide electric fields (Eox) around 8.5 MV/cm to 9 MV/cm for all commercial MOSFETs. Gate leakage currents and threshold voltage shifts are also monitored under different oxide fields (Eox = 8 MV/cm and 10 MV/cm). The results suggest the failure mode under high oxide electric field is modified by impact ionization or Anode Hole Injection (AHI) induced hole trapping. This observation agrees with previously published oxide reliability studies on SiC MOSFETs and suggests that constant-voltage TDDB measurements need to be carefully performed under low oxide fields to avoid lifetime overestimation caused by hole trapping. The extrapolated t 63% lifetimes (times to 63% failures) from TDDB measurements performed at Eox < 8.5 MV/cm are longer than 10 8 hours at 150°C for all vendors. The predicted lifetimes at Eox = 4 MV/cm demonstrate more than 10 5 times increases than the oxide lifetimes reported a decade ago, showing promising progress in SiC technology.Index Terms-Electron and hole trapping, impact ionization, gate oxide reliability, lifetime, silicon carbide (SiC) power MOS-FETs, time-dependent dielectric breakdown (TDDB).