In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

Abstract:This paper describes the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material. In the past decade research has identified carbon-based electronics as a possible alternative to silicon-based electronics. This enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic carbon, can overcome some of these problems and therefore is a promising new electronic material.Although graphene devices have been built before, in this work we provide the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods. Graphene devices presented feature high-k dielectric, mobilities up to 5000 cm 2 /Vs and, I on /I off ratios of up to 7, and are methodically analyzed to provide insight into the substrate properties.Typical of graphene, these micron-scale devices have negligible band gaps and therefore large leakage currents.NOTE: This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible.

We have developed an implantable fuel cell that generates power through glucose oxidation, producing steady-state power and up to peak power. The fuel cell is manufactured using a novel approach, employing semiconductor fabrication techniques, and is therefore well suited for manufacture together with integrated circuits on a single silicon wafer. Thus, it can help enable implantable microelectronic systems with long-lifetime power sources that harvest energy from their surrounds. The fuel reactions are mediated by robust, solid state catalysts. Glucose is oxidized at the nanostructured surface of an activated platinum anode. Oxygen is reduced to water at the surface of a self-assembled network of single-walled carbon nanotubes, embedded in a Nafion film that forms the cathode and is exposed to the biological environment. The catalytic electrodes are separated by a Nafion membrane. The availability of fuel cell reactants, oxygen and glucose, only as a mixture in the physiologic environment, has traditionally posed a design challenge: Net current production requires oxidation and reduction to occur separately and selectively at the anode and cathode, respectively, to prevent electrochemical short circuits. Our fuel cell is configured in a half-open geometry that shields the anode while exposing the cathode, resulting in an oxygen gradient that strongly favors oxygen reduction at the cathode. Glucose reaches the shielded anode by diffusing through the nanotube mesh, which does not catalyze glucose oxidation, and the Nafion layers, which are permeable to small neutral and cationic species. We demonstrate computationally that the natural recirculation of cerebrospinal fluid around the human brain theoretically permits glucose energy harvesting at a rate on the order of at least 1 mW with no adverse physiologic effects. Low-power brain–machine interfaces can thus potentially benefit from having their implanted units powered or recharged by glucose fuel cells.

Figure 1: The thin-body silicide source/drain MOSFET in cross section. Source/drains are made in 100Å Si: NMOS uses ErSi1.7 (Φb0n=0.28V), PMOS uses PtSi (Φb0p=0.24V). Spacer thickness is limited to 100Å, in order to guarantee that the metal diffuses underneath the gate. Complementary silicide source/drain thin-body

No abstract

No abstract

Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel "Folded Channel Transistor" structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SO1 MOSFETs [1], [2] simplified the fabrication process. The special features of thie structure ( Fig. 1) are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short. Figure 2 shows the process flow and the SEM pictures at two fabrication steps. Using SO1 wafers as the starting material, Si3N4 and Si02 layer were deposited on the 50-nm SO1 layer. Using 100 keV EB lithography and ashing technique, -20 nm wiide Si fins were patterned and etched. Then, 100-nm P-doped a-Si and 300-nm Si02 were deposited and the result is shown in the top SEM picture. The a-Si becomes polycrystalline later and provides a good contact at the side surface of the Si fin. After delineating the a-Si S/D pattern, SiOz spacers were formed on the sidewalls of the S/D. Through sufficient over-etching, Si02 was removed from the sides of the relatively low Si fins. The top-view SEM picture shows a 15-nm thin Si fin visible in the 50-nm spacer gap, which determines the gate length. After growing 2.5-nm gate oxide on the side surfaces of the Si fin, B-in-situ-doped SiGe (60% Ge) was deposited as the gate. During the gate oxidation, P was diffused from the raised S/D into the Si fin region tlo form S/D extension. We did not use metal electrodes in this experiment so that additional S/D extension diffusion can be optimized. This explains the large parasitic resistance of over 3000 ohmldevice. The W of the devices is twice the height of the Si fins or approximately 100 nm.Typical I-V characteristics of 30-nm gate length are slhown in Fig. 3. In spite of low channel impurity concentration ( 10l6 cm-'), the leakage current caused by DIBL was well suppressed. The Vt roll-off characteristics of a 20-nm Si width devices are shown in Fig. 4. Vt is defined as the gate voltage when Ids= lo-'' A. Good roll-off characteristics are observed for folded channel structure. Figure 5 shows the subthreshold swing dependence on the: Si width. Since the thin body of the double-gate device prevents the punch-through, the folded channel devices show small swings. In Fig. 6, the transconductance (Gm) are plotted with the Si width as a parameter. Interestingly, Gm peaks at 30-nm of Si width. This is because that the thin body increases the parasitic resistance but also can increase the mobility and reduce the charge centrioid, resulting in an optimum in the Si width. Finally, to achieve high current drivability and demonstrate dis...

Inorganic chemistry Z 0100Silicon Device Scaling to the Sub-10-nm Regime -[32 refs.]. -(IEONG*, M.; DORIS, B.; KEDZIERSKI, J.; RIM, K.; YANG, M.; Sci.