In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.
We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6nm and SO1 channels as thin as 4nm are presented. For the frst time, we report ring oscillators with 26nm gate lengths and ultra-thm Si channels.10.6.2
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The authors have examined the role of sub nanometer La2O3 and LaN cap layers interposed in Si∕HfO2∕TiN high-k gate dielectric stacks in tuning the flatband and threshold voltages of capacitors and transistors. High performance, band edge n metal oxide field effect transistors with channel lengths down to 60nm may be fabricated without significant compromise in mobility, electrical thickness, and threshold voltage. They have carried out a microstructural evaluation of these stacks and correlated these results with the electrical behavior of the devices.
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