A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Zafar, Sufi; Kim, Y.H.; Narayanan, V.; Cabral, C.; Paruchuri, Vamsi; Doris, B.; Stathis, James H.; Callegari, A.; Chudzik, M.

doi:10.1109/vlsit.2006.1705198

Cited by 166 publications

(95 citation statements)

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“…NBTI manifests itself as a temporal increase in the threshold voltage, Î Ø , of a PMOS transistor, thereby causing circuit delays to degrade over time and exceed their specifications. A corresponding and dual effect, known as Positive Bias Temperature Instability (PBTI) [1]- [3], is seen for NMOS devices, when a positive bias stress is applied across the gate oxide of the NMOS device. Although the impact of PBTI is lower than NBTI [2], it is increasingly becoming important in its own right, particularly with the use of Hf-based high-k gate oxides for leakage reduction [1], [3].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Kumar

Kim

Sapatnekar

2011

IEEE Trans. VLSI Syst.

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Abstract-Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in NMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.

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Section: Introductionmentioning

confidence: 99%

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Kumar

Kim

Sapatnekar

2011

IEEE Trans. VLSI Syst.

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“…The BTI aging is usually considered in two different phases: stress and recovery. Several models have predicted the V T shift in devices [10,11] caused by BTI. Since our work is an analysis during a long period of time we simplify the model, explained in detail as follows.…”

Section: Bti Aging Stress and Recovery Phase Parametersmentioning

confidence: 99%

“…Since our work is an analysis during a long period of time we simplify the model, explained in detail as follows. Note that, we have assumed high-k transistors in our work where both N and P transistors experience BTI aging [10].…”

Section: Bti Aging Stress and Recovery Phase Parametersmentioning

confidence: 99%

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Pouyan

Amat

Barajas

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

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“…However, for high-k/metal-gate nMOS transistors with significant charge trapping, the PBTI effect can no longer be ignored. In fact, it has been shown that the PBTI effect is more significant than the NBTI effect on 32-nm high-k/metal-gate processes [1]- [2]. Traditional circuits use critical path delay as the overall circuit clock cycle in order to perform effectively.…”

Section: Introductionmentioning

confidence: 99%

A Review on aging aware Reliable Multiplier

Sawant¹,

Badhe²

2017

International Journal of Advanced Research in Computer and Comm

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Advanced Digital multipliers are the most critical arithmetic functional units. The general execution of these systems depends on the throughput of the multiplier. While negative bias temperature instability (NBTI) effects on logic gates are of major concern for the reliability of digital circuits, they become even more critical when considering the components for which even minimal parametric variations affect the lifetime of the overall circuit. In the mean time, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (V gs=−Vdd), increasing the threshold voltage of the pMOS transistor, and decresing multiplier speed. A similar phenomenon, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both effects or impacts reduce transistor speed, and in the long term, the system may fail because of timing infringement. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier can give higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect.Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.

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A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Cited by 166 publications

References 0 publications

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

A Review on aging aware Reliable Multiplier

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