This paper analyses how a single metal-oxide-semiconductor field-effect transistor (MOSFET) can be employed as a thermal sensor to measure on-chip dynamic thermal signals caused by a power-dissipating circuit under test (CUT). The measurement is subjected to two low-pass filters (LPF). The first LPF depends on the thermal properties of the heat-conduction medium (i.e. silicon) and the CUT-sensor distance, whereas the second depends on the electrical properties of the sensing circuit such as the bias current and the dimensions of the MOSFET sensor. This is evaluated along the paper through theoretical models, simulations, and experimental data resulting from a chip fabricated in 0.35 mu m CMOS technology. Finally, the proposed thermal sensor and the knowledge extracted from this paper are applied to estimate the linearity of a radio-frequency (RF) amplifier. (C) 2016 Elsevier B.V. All rights reserved.Peer ReviewedPostprint (author's final draft
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 µm 2 .
Abstract-The viability of using off-chip single-shot imaging techniques for local thermal testing in integrated Radio Frequency (RF) power amplifiers (PA's) is analyzed. With this approach, the frequency response of the output power and power gain of a Class A RF PA is measured, also deriving information about the intrinsic operation of its transistors. To carry out this case study, the PA is heterodynally driven, and its electrical behavior is down converted into a lower frequency thermal field acquirable with an InfraRed Lock-In Thermography (IR-LIT) system. After discussing the theory, the feasibility of the proposed approach is demonstrated and assessed with thermal sensors monolithically integrated in the PA. As crucial advantages to RF-testing, this local approach is noninvasive and demands less complex instrumentation than the mainstream commercially available solutions.
Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.
Aging produced by both DC and RF stress is experimentally analyzed on a RF CMOS power amplifier. The selected circuit topology allows observing individual NMOS and PMOS transistors degradations, as well as the aging effect on the circuit functionality. A direct relation between DC and RF (gain) parameters has been observed. NMOS degradation (both in mobility and V th ) is stronger than that of the PMOS, which identifies the NMOS as the main cause of the RF degradation in this circuit.
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