This paper presents two approaches to characterize RF circuits with built-in differential temperature measurements, namely the homodyne and heterodyne methods. Both non-invasive methods are analyzed theoretically and discussed with regard to the respective trade-offs associated with practical off-chip methodologies as well as on-chip measurement scenarios. Strategies are defined to extract the center frequency and 1 dB compression point of a narrow-band LNA operating around 1 GHz. The proposed techniques are experimentally demonstrated using a compact and efficient on-chip temperature sensor for built-in test purposes that has a power consumption of 15 μW and a layout area of 0.005 mm 2 in a 0.25 μm CMOS technology. Validating results from off-chip interferometer-based temperature measurements and conventional electrical characterization results are compared with the on-chip measurements, showing the capability of the techniques to estimate the center frequency and 1 dB compression point of the LNA with errors of approximately 6% and 0.5 dB, respectively.
In this paper we demonstrate that the steady state temperature increase due to the power dissipated by the circuit under test can be used as observable to test the gain of a 2GHz linear class A Power Amplifier. As a proof of concept, we use two strategies to monitor the temperature: a temperature sensor embedded within the same silicon die, which can be used for a BIST approach, and an Infra Red camera, with applications to failure analysis and product debugging.Peer ReviewedPostprint (published version
This letter introduces a novel on-chip measurement technique for the determination of the central frequency and 3 dB bandwidth of a 60 GHz power amplifier (PA) by performing low frequency temperature measurements. The temperature sensor is embedded in the same silicon die as the PA, and placed in empty spaces next to it. Results confirm that temperature sensors can be used as functional built-in testers which serve to reduce testing costs and enhance yield as part of self-healing strategies.Index Terms-Built-in test, CMOS millimeter wave integrated circuits, design for testability, frequency response, temperature measurement.
Statistical characterization of CMOS transistor variability phenomena in modern nanometer technologies is key for accurate end-of-life prediction. This paper presents a novel CMOS transistor array chip to statistically characterize the effects of several critical variability sources, such as time-zero variability (TZV), random telegraph noise (RTN), bias temperature instability (BTI), and hot-carrier injection (HCI). The chip integrates 3136 MOS transistors of both pMOS and nMOS types, with eight different sizes. The implemented architecture provides the chip with a high level of versatility, allowing all required tests and attaining the level of accuracy that the characterization of the above-mentioned variability effects requires. Another very important feature of the array is the capability of performing massively parallel aging testing, thus significantly cutting down the time for statistical characterization. The chip has been fabricated in a 1.2-V, 65-nm CMOS technology with a total chip area of 1800 × 1800 µm 2 .
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