Abstract-The demand for highly scalable and low power memory has led to research in emerging technologies and devices. Among these devices, memristors has attracted increased attention as being a promising storage device. However, due to its nano-scale size it faces various types of reliability issues. In this study, we have reviewed the memristive mechanisms and reliability concerns existing in memristor memory design. Then, we have simulated the ionic drift memristor model in presence of the process variability. Next, by considering a normal distribution for the resistive distribution of memristors in LRS and HRS state we have shown the instabilities and probability of failure in read and write procedure of memristive memories, and highlighted the requisite and motivation for the reliability aware memristive circuit design.

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Summary The power and reliability issues of today's memories (static and dynamic RAMs) reduce the advances achieved by their implementation in scaled technology. There are several emergent memory technologies that address the technical constraints of today's memories, among which the most promising solutions are the resistance‐based memories, such as phase change memories, the redox‐based resistive memories, and the spin‐transfer torque magnetic memories. These technologies are facing various challenges that have to be addressed to render them efficient in today's applications. Until recently, research focus was on the design for performance and power efficiency, but lately, the test and reliability issues of these devices have become of major concern to the community. This paper presents an overview of the challenges and proposed test and reliability boost solutions developed to suit the needs of the emerging memories under analysis. It underlines (1) the unique faults that occur in the memory cell due to known issues in the emerging storage devices, (2) the dedicated solutions developed for efficient testing of the emerging memories under study, (3) the main reliability concerns related to the emerging storage devices, and (4) the design solutions targeted at mitigating these reliability issues. Copyright © 2017 John Wiley & Sons, Ltd.

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Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbarbased memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65% in comparison with non-adaptive reconfiguration strategy.

Abstract-Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.

This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.