Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime

Pouyan, Peyman; Amat, E.; Rubio, Antonio

doi:10.1109/vts.2012.6231060

Cited by 15 publications

(12 citation statements)

References 17 publications

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“…The adaptive proactive approach balances the activity distribution between all SRAM cells, thus demonstrating the benefits of using adaptive recovery phase ratios during the columns' lifetime. It can extend SRAM memory columns' lifetime in comparison with no-adaptive proactive memories [8]. Also while the no proactive memories need to increase the Vmin of the memory to keep it functional, our approach can reduce this Vmin drift (because of slower SNM drop) along a specific period of time (5 years in our analysis).…”

Section: Adaptive Proactive Approach In Presence Of Single Vddmentioning

confidence: 96%

“…All the memory columns will experience recovery periods along their lifetime by a round robin method in which all columns (spare and operational columns) participate in the memory operation and have recovery ratios in function of their V T and SNM value, affected by process variation and BTI degradation [8]. We implement our approach in Matlab by generating random V T s and calculating each cell SNM at time zero.…”

Section: Adaptive Proactive Approach In Presence Of Single Vddmentioning

confidence: 99%

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Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Pouyan

Amat

Barajas

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.

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Section: Adaptive Proactive Approach In Presence Of Single Vddmentioning

confidence: 96%

Section: Adaptive Proactive Approach In Presence Of Single Vddmentioning

confidence: 99%

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Pouyan

Amat

Barajas

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

Self Cite

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show abstract

“…The reconfiguration techniques can be differentiated into two main categories: 1-Reactive, 2-Proactive [12,13]. The former can be based on conventional repair techniques such as row/column replacement of faulty one with a spare one [12].…”

Section: Reconfiguration In Memristive Crossbarmentioning

confidence: 99%

“…In such an approach the use of spare units is limited only to the time that a fail occurs. Another approach is based on the utilization of spare and operational units together with the highest simultaneity and is called the proactive reconfiguration [13]. This presents a relevant enhancement of the system performance and for this we have chosen as a baseline configuration.…”

Section: Reconfiguration In Memristive Crossbarmentioning

confidence: 99%

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Statistical lifetime analysis of memristive crossbar matrix

Pouyan¹,

Amat²,

Rubio³

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Abstract-Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.

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Impact and mitigation of SRAM read path aging

Agbo

Taouil

Kraak

et al. 2018

Microelectronics Reliability

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This paper proposes an appropriate method to estimate and mitigate the impact of aging on the read path of a 32 nm high performance SRAM design; it analyzes the impact of the memory cell, and sense amplifier (SA), and their interaction. The method considers different workloads and inspects both the bit-line swing (which reflect the degradation of the cell) and the sensing delay (which reflects the degradation of the sense amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results with respect to the quantification of the aging, show for the considered SRAM read-path design that the cell degradation is marginal as compared to the sense amplifier, while the sensing delay degradation strongly depends on the workload, supply voltage and temperature (up to 41% degradation). The mitigation schemes, one targeting the cell and one the sense amplifier, confirm the same and show that sense amplifier mitigation is more effective for the SRAM read path than cell mitigation.

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Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetime

Cited by 15 publications

References 17 publications

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches

Statistical lifetime analysis of memristive crossbar matrix

Impact and mitigation of SRAM read path aging

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