Statistical lifetime analysis of memristive crossbar matrix

Pouyan, Peyman; Amat, E.; Rubio, Antonio

doi:10.1109/dtis.2015.7127378

Cited by 13 publications

(6 citation statements)

References 11 publications

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“…The r 1 to r N-1 are random numbers betw een 0 and 1. These random numbers are created as follow s: 1-Create m random numbers that sum up 1 2-Repeat step 1 α times, where α =N/m and make a set of random numbers (r 1 to r N ) 3-Use N-1 terms of the above set (r 1 to r N-1 ) for the calculation in (13) N ext, E(0) i s ev aluated mathematically from (18) and the above process (steps 1-3) i s repeated 10,000 times, each time with a different set of random portions (r 1 -r 2 ,….,r N-1 ). At the end all E(0) values are averaged from each iteration and the expected number of shifts in this scenario i s obtained.…”

Section: Finding the Number Of Shifts In Non-uniform Assumption Usingmentioning

confidence: 99%

“…They will affect the normal operation of memory cell because for instance, process variability could cause variation in the nominal high and low re-si stance values, or endurance degradation will impose dynamic variation to the resi stance values due to aging mechanisms [12]. H aving these reliability considerations, it becomes necessary to analytically model and estimate the lifetime of memristive devices in presence of process variability and endurance degradation and then to design new and innovative architectures to overcome these draw back s [13]. At this point, one of the main interests for the researcher s is to design reconfigurable crossbarbased memory architectures.…”

Section: Introductionmentioning

confidence: 99%

“…At this point, one of the main interests for the researcher s is to design reconfigurable crossbarbased memory architectures. Therefore, w e have extended our work in [13] by proposing innovative reconfiguring approaches to extend the memristive crossbar-based memory lifetime, and al so comparing their efficiency in terms of lifetime extension.…”

Section: Introductionmentioning

confidence: 99%

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Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Pouyan

Amat

Rubio

2018

IEEE Trans. Emerg. Topics Comput.

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Among the emerging technologies and devices for highly scalable and low power memory architectures, memristors are considered as one of the most favorable alternatives for next generation memory technologies. They are attracting great attention recently, due to their many appealing characteristics such as non-volatility and compatibility with CMOS fabrication process. But beside all memristor advantages, their drawbacks including manufacturing process variability and limited read/write endurance, could risk their future utilization. This paper will evaluate the impact of reliability concerns in lifetime of memristive crossbars and will present the design basis of two proposed reconfiguration approaches in memristive crossbarbased memories, in order to extend the system lifetime by utilizing available resources in an intense way and without need of failure recovery. It is observed that the adaptive reconfiguring approach can improve the crossbar reliability and extend its lifetime up to 65% in comparison with non-adaptive reconfiguration strategy.

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Section: Finding the Number Of Shifts In Non-uniform Assumption Usingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Pouyan

Amat

Rubio

2018

IEEE Trans. Emerg. Topics Comput.

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“…Crossbar architectures are attractive due to the regularity and the integration density. They have become more popular for memristive devices for these reasons [5,19,36,37]. It has previously been shown that a general memcapacitive crossbar network can be built [45] and that such a crossbar network can perform a dot product [13].…”

Section: Memcapacitive Crossbar Classifiermentioning

confidence: 99%

Memcapacitive Devices in Logic and Crossbar Applications

Tran¹,

Teuscher²

2017

Preprint

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Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7× less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1, 500× for the MNIST dataset and a factor of about 1, 000× for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications.

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“…Figure 3 shows the probability of failure when considering Reference=(LRS+HRS)÷2. The wide resistance distribution of RRAM cells can impose low read yields and can reduce the device lifetime [16], therefore it is needed to design variability tolerant circuits, presented in the next section.…”

Section: B Impact Of Rram Variabilitymentioning

confidence: 99%

RRAM variability and its mitigation schemes

Pouyan

Amat

Hamdioui

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.

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Statistical lifetime analysis of memristive crossbar matrix

Cited by 13 publications

References 11 publications

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Memristive Crossbar Memory Lifetime Evaluation and Reconfiguration Strategies

Memcapacitive Devices in Logic and Crossbar Applications

RRAM variability and its mitigation schemes

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