Reliability challenges in design of memristive memories

Pouyan, Peyman; Amat, E.; Rubio, Antonio

doi:10.1109/vari.2014.6957074

Cited by 42 publications

(16 citation statements)

References 18 publications

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“…Values of the parameters of the model were set as: {a, b, c, m, f 0 , L 0 } = {15000, 0, 0.1, 82, 310}, with R OFF = 200KΩ, and R ON = 2KΩ. Variation of switching thresholds (i.e., V SET,RESET ± v o ) should ideally be minimized as much as possible to ensure high reliability [34], [35]. In the simulations, the threshold values V SET = |V RESET | = 0.3V were used as mean values of normal distributions with a small standard deviation, which we then used to decide on the proper programming pulse amplitudes.…”

Section: Spice Simulation Resultsmentioning

confidence: 99%

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Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

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Aquesta és una còpia de la versió draft d'un article publicat a IEEE transactions on nanotechnologyhttp://hdl.handle.net/2117/104473 Papandroulikadis, G., Vourkas, I., Abustelema, A., Sirakoulis, G., Rubio, A. Crossbar-based memristive logic-in-memory architecture. "IEEE transactions on nanotechnology", 1 Abril 2017, vol. 16, núm. 3, p. 491-501. DOI: 10.1109/TNANO.2017 © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1Abstract-The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We present an analysis of circuit resources, integration density, and logic computation parallelism and prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder (HA) and sum-of-products logic functions.

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Section: Spice Simulation Resultsmentioning

confidence: 99%

“…Given the need to be able to perform as many parallel computations as possible, using a different SL geometry would not work due to current leakage/sneak-paths [32], [34], which contribute to incorrect computations and/or increases in power consumption. For example, neither row nor column SLs would work with our approach.…”

Section: ) Twisted Sl Driving Patternsmentioning

confidence: 99%

Crossbar-Based Memristive Logic-in-Memory Architecture

Papandroulidakis

Vourkas

Abusleme

et al. 2017

IEEE Trans. Nanotechnology

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“…Another possible solutions are discussed in [47] and [48]. It is recognized that other reliability challenges may exist due to variability of resistance, as discussed in [49]; however, these issues are outside the scope of this paper.…”

Section: Emerging Versus Traditional Memory Technologies Power Anmentioning

confidence: 98%

Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications

Halawani

Mohammad

Homouz

et al. 2016

IEEE Trans. VLSI Syst.

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Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin-transfer torque (STT)-RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and lowvoltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT-RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT-RAM power has been compared with the traditional sixtransistor-SRAM-based memory power and potential application in wireless sensor nodes is explored. This paper uses 45-nm foundry process technology data for SRAM and physics-based mathematical models derived from real devices for memristor and STT-RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT-RAM, respectively, at 1% duty cycle.Index Terms-Duty cycle, embedded memory, low energy, low power, memristor, spin-transfer torque (STT)-RAM, wireless sensor node (WSN).

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“…The correct operation of memory depends on the precise Read/Write process, nevertheless the existing variability can disturb them and reduce the memory yield [13].…”

Section: B Impact Of Rram Variabilitymentioning

confidence: 99%

RRAM variability and its mitigation schemes

Pouyan

Amat

Hamdioui

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.

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Reliability challenges in design of memristive memories

Cited by 42 publications

References 18 publications

Crossbar-Based Memristive Logic-in-Memory Architecture

Crossbar-Based Memristive Logic-in-Memory Architecture

Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications

RRAM variability and its mitigation schemes

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