Test and Reliability of Emerging Non-volatile Memories

Hamdioui, Said; Pouyan, Peyman; Li, Huawei; Wang, Ying; Raychowdhur, Arijit; Yoon, Insik

doi:10.1109/ats.2017.42

Cited by 14 publications

(10 citation statements)

References 52 publications

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“…2) BIST Techniques: BIST techniques presented in [80]- [82] were developed to perform in situ, statistical, retention failure testing of large STT-MRAM arrays.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

“…In order to alleviate the retention test time problem, Yoon et al [80], Yoon and Raychowdhury [81], and Hamdioui et al [82] proposed a new MBIST architecture that performs retention testing of large STT-MRAM arrays in a time-efficient manner. The proposed MBIST scheme reduces retention time considerably by: 1) applying weak write current to multiple rows in an array and 2) conducting a read operation only when a fault is detected within the rows under test.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

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A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

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“…2) BIST Techniques: BIST techniques presented in [80]- [82] were developed to perform in situ, statistical, retention failure testing of large STT-MRAM arrays.…”

Section: ) Test Generation Methodsmentioning

confidence: 99%

Section: ) Test Generation Methodsmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

View full text Add to dashboard Cite

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“…To further optimize the test time, one can also incorporate DfT; e.g., DfT that enables the test of many faults simultaneously, parallel testing, etc. [208][209][210].…”

Section: Device-aware Test Developmentmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…To further optimize the test time, one can also incorporate DfT; e.g., DfT that enables the test of many faults simultaneously, parallel testing, etc. [27,31,32].…”

Section: Test Developmentmentioning

confidence: 99%

Device-Aware Test: A New Test Approach Towards DPPB Level

Fieback

Medeiros

et al. 2019

2019 IEEE International Test Conference (ITC)

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This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach suggests), but it rather incorporates the impact of the physical defect on the technology parameters of the device and thereafter on its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis (based on fault simulation) is performed to derive appropriate fault models and subsequently test solutions. The approach is demonstrated using two memory technologies: resistive random access memory (RRAM) and spintransfer torque magnetic random access memory (STT-MRAM). The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level. The new approach clearly sets up a turning point in testing for at least the considered two emerging memory technologies.

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Test and Reliability of Emerging Non-volatile Memories

Cited by 14 publications

References 52 publications

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Device-Aware Test: A New Test Approach Towards DPPB Level

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