We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a Wbased SOT underlayer have very large endurance (> 5x10 10 ), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Introduction: The introduction of non-volatility (NV) at the cache level in advance logic nodes is sought as it would lead to a large decrease of the power consumption of microprocessors. Among NV memory technologies, spin-transfer torque (STT) MRAM has gained a lot of attention due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. Despite all these advantages, STT-MRAM cannot operate reliably at ns and sub-ns scales due to large incubation delays [1,2], making it an unsuitable solution to tackle L1/2 SRAM cache replacement. In addition, the shared read/write path can impair the read reliability, while the write current can impose severe stress on the MTJ, leading to time dependent degradation of the memory cell. To mitigate these issues, spin-orbit torque (SOT)-MRAM has been recently proposed [2,3]. SOT induces switching of the free layer (FL) of the MTJ by injecting an in-plane current in an adjacent SOT layer, typically with the assistance of a static in-plane magnetic field [2]. This enables a three terminal MTJ-based concept that isolates the read/write path (Fig. 1), significantly improving the device endurance and read stability. Moreover, due to SOT spin transfer geometry, incubation time is negligible which allows for reliable switching operation at sub-ns timescales [4,5]. Here, we report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. We demonstrate low power sub-ns switching and pathways for further optimization. Finally, excellent endurance and absence of electro-migration effect of ultrathin SOT layers are shown.Integration flow: We used a SOT dedicated mask set in the imec 300 mm fab. The main steps of the integration process are summarized in Fig. 2: a SOT-MTJ stack is deposited on smooth bottom electrodes (BE), which are fabricated using a tungsten (W) damascene process. The MTJ is top pinned and consist of SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized (PMA) stack, where the SOT layer is W-based. Specific stop etch conditions have been developed to leave the SOT layer intact while patterning the MTJ pillar without producing sidewall shorts across the MgO barrier (Fig. 2c,d). Subsequently, the SOT layer is etched to form the three terminal device and a dual damascene Cu top electrode (TE) was fabricated to complete the electrical connection ( Fig. 2a).Stack development: SOTs possess a damping-like term (τDL) attributed to spin Hall and a field-like term (τFL) attributed to interface interactions [2]. Recent work indicates that τDL triggers switching while τFL accelerates it [5]. Charge-to-spin conversion efficiency parameters θDL and...

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This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach suggests), but it rather incorporates the impact of the physical defect on the technology parameters of the device and thereafter on its electrical parameters. Once the defective electrical model is defined, a systematic fault analysis (based on fault simulation) is performed to derive appropriate fault models and subsequently test solutions. The approach is demonstrated using two memory technologies: resistive random access memory (RRAM) and spintransfer torque magnetic random access memory (STT-MRAM). The results show that the proposed approach is able to sensitize faults for defects that are not detected with the traditional approach, meaning that the latter cannot lead to high-quality test solutions as required for a defective part per billion (DPPB) level. The new approach clearly sets up a turning point in testing for at least the considered two emerging memory technologies.

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOScompatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development. Introduction: Among non-volatile memory technologies, Spin-Transfer-Torque (STT) MRAM is seen as a credible candidate to replace SRAM in low level caches due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. This is reflected by major foundries and tool suppliers investing significant R&D resources into embedded MRAM past years. Recently they even started prototyping demonstrators, progressively reaching maturity for mass production [1-5]. However, STT-MRAM

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