SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories

Abstract

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a Wbased SOT underlayer have very large endurance (> 5x10 10 ), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Introduction: The introduction of non-volatility (NV) at the cache level in advance logic nodes is sought as it would lead to a large decrease of the power consumption of microprocessors. Among NV memory technologies, spin-transfer torque (STT) MRAM has gained a lot of attention due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. Despite all these advantages, STT-MRAM cannot operate reliably at ns and sub-ns scales due to large incubation delays [1,2], making it an unsuitable solution to tackle L1/2 SRAM cache replacement. In addition, the shared read/write path can impair the read reliability, while the write current can impose severe stress on the MTJ, leading to time dependent degradation of the memory cell. To mitigate these issues, spin-orbit torque (SOT)-MRAM has been recently proposed [2,3]. SOT induces switching of the free layer (FL) of the MTJ by injecting an in-plane current in an adjacent SOT layer, typically with the assistance of a static in-plane magnetic field [2]. This enables a three terminal MTJ-based concept that isolates the read/write path (Fig. 1), significantly improving the device endurance and read stability. Moreover, due to SOT spin transfer geometry, incubation time is negligible which allows for reliable switching operation at sub-ns timescales [4,5]. Here, we report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. We demonstrate low power sub-ns switching and pathways for further optimization. Finally, excellent endurance and absence of electro-migration effect of ultrathin SOT layers are shown.Integration flow: We used a SOT dedicated mask set in the imec 300 mm fab. The main steps of the integration process are summarized in Fig. 2: a SOT-MTJ stack is deposited on smooth bottom electrodes (BE), which are fabricated using a tungsten (W) damascene process. The MTJ is top pinned and consist of SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized (PMA) stack, where the SOT layer is W-based. Specific stop etch conditions have been developed to leave the SOT layer intact while patterning the MTJ pillar without producing sidewall shorts across the MgO barrier (Fig. 2c,d). Subsequently, the SOT layer is etched to form the three terminal device and a dual damascene Cu top electrode (TE) was fabricated to complete the electrical connection ( Fig. 2a).Stack development: SOTs possess a damping-like term (τDL) attributed to spin Hall and a field-like term (τFL) attributed to interface interactions [2]. Recent work indicates that τDL triggers switching while τFL accelerates it [5]. Charge-to-spin conversion efficiency parameters θDL and...

The spin Hall effect of Bi-Sb alloys driven by thermally excited Dirac-like electrons

“…To compare the efficiency of BiSb with other materials system, we substitute typical values of the relevant parameters and estimate I c . We compare BiSb/CoFeB with W/CoFeB [69], the latter being the prototype of SOT-MRAM [70]. The parameters assumed are:…”

“…SOT measurements of a standard sample: Pt/CoFeB.References[61][62][63][64][65][66][67][68][69][70].Acknowledgements: We thank Y. Fuseya, H. Kohno, G. Qu for helpful discussions.…”

Energy‐Efficient Ultrafast SOT‐MRAMs Based on Low‐Resistivity Spin Hall Metal Au0.25Pt0.75

“…random access memory (MRAM) with large perpendicular magnetic anisotropy is attractive for its good scalability and high thermal stability [4,5] during fast sub-nanosecond write, [6] the required high write current density can exert severe stress on the magnetic tunnel junction (MTJ) and induce wear-out and breakdown of the MTJ barrier, [7] leading ultimately to degradation of the memory cell. Meanwhile, the shared read/write path can lead to write upon read errors.…”

“…An alternative, 3-terminal spin-orbit torque (SOT) MRAM [8,9] has the potential to mitigate these issues. [7,[14][15][16][17] SOT-MRAMs based on a spin Hall metal that combines a giant spin Hall ratio (θ SH ) with a relatively low resistivity (ρ xx ) can also have unlimited endurance due to the suppression of Joule heating induced bursting and migration of the write line [2] as well as low values of write impedance that is compatible with superconducting circuits in cryogenic computing systems. The nonvolatile SOT-MRAMs can have long data retention, zero standby power, and fast and reliable write.…”

“…Interface engineering has already been demonstrated to significantly reduce both α and 4πM eff of the Fe 0.6 Co 0.2 B 0.2 free layer. The write current and the write power can be further reduced by additional factors of 3 and >18 by using more aggressive industry-level lithography to narrow the spin Hall channel from 300 to below 100 nm [27,37] and to shorten it from 1.2 µm to 200 nm, [7] and by replacing the magnetic stacks in the "via" regions (see Figure 1c and Figure S2, Supporting Information) with highly conductive materials. As shown in Figure S5, Supporting Information, we have found that a Pt 0.5/ Hf 0.25 bilayer can effectively suppress α contributed by the interfacial spin-orbit coupling via spin memory loss [19] and two-magnon scattering, [22] despite that the 0.5 nm-thick Hf single-layer spacer that was inserted at the bottom of the 1.4 nm Fe 0.6 Co 0.2 B 0.2 free layer appears ineffective in doing so www.advelectronicmat.de probably because Hf does not wet Au surface and forms a discontinuous layer.…”