Current-induced spin-transfer torques (STT) and spin-orbit torques (SOT) enable the electrical switching of magnetic tunnel junctions (MTJs) in nonvolatile magnetic random access memories. In order to develop faster memory devices, an improvement of the timescales underlying the currentdriven magnetization dynamics is required. Here we report all-electrical time-resolved measurements of magnetization reversal driven by SOT in a three-terminal MTJ device. Single-shot measurements of the MTJ resistance during current injection reveal that SOT switching involves a stochastic two-step process consisting of a domain nucleation time and propagation time, which have different genesis, timescales, and statistical distributions compared to STT switching. We further show that the combination of SOT, STT, and voltage control of magnetic anisotropy (VCMA) leads to reproducible sub-ns switching with a spread of the cumulative switching time smaller than 0.2 ns. Our measurements unravel the combined impact of SOT, STT, and VCMA in determining the switching speed and efficiency of MTJ devices. Switching nanomagnets by current injection offers unparalleled scalability, as well as low power and high speed operation compared to control via external magnetic fields 1-3. Spin-transfer torques (STT) 1,4 are presently employed in memory and spin logic applications 5,6 to control the state of magnetic tunnel junctions (MTJ) via an electric current passing through the reference and free magnetic layers, which allows also for efficient readout of the MTJ through the tunnel magnetoresistance (TMR). Time-resolved studies of magnetization reversal in spin valve 7,8 and MTJ devices 9-12 have shown that STT enables switching on a timescale of 100 to 1 ns, depending on the driving current 13 and external field 14. However, STT switching is characterized by nonreproducible dynamic paths and incubation times up to several tens of ns long, which limit the reliability and speed of the reversal process to about 10-20 ns, even when mitigation strategies based on large driving currents or noncollinear spin injection are employed 13,15,16. These limitations may be overcome by magnetization reversal driven by spin-orbit torques (SOT) 3,17-19 , which has been recently demonstrated in three-terminal MTJs with in-plane 20,21 as well as out-of-plane magnetization 22-25. SOT switching combines an in-plane current injection geometry with charge-to-spin conversion due to the spin Hall effect and interfacial spin scattering 3. Such a geometry decouples the write and read current paths, improving the MTJ endurance and operation speed by minimizing electrical stress of the tunnel barrier and allowing for tuning the barrier thickness for high TMR, fast read-out, and minimal read disturbances. Moreover, in devices with perpendicular magnetization, the injected spin current is orthogonal to the quiescent magnetization of the free layer, thus providing an "instant on" torque that is expected to minimize the switching incubation time 25-27 .

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a Wbased SOT underlayer have very large endurance (> 5x10 10 ), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Introduction: The introduction of non-volatility (NV) at the cache level in advance logic nodes is sought as it would lead to a large decrease of the power consumption of microprocessors. Among NV memory technologies, spin-transfer torque (STT) MRAM has gained a lot of attention due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. Despite all these advantages, STT-MRAM cannot operate reliably at ns and sub-ns scales due to large incubation delays [1,2], making it an unsuitable solution to tackle L1/2 SRAM cache replacement. In addition, the shared read/write path can impair the read reliability, while the write current can impose severe stress on the MTJ, leading to time dependent degradation of the memory cell. To mitigate these issues, spin-orbit torque (SOT)-MRAM has been recently proposed [2,3]. SOT induces switching of the free layer (FL) of the MTJ by injecting an in-plane current in an adjacent SOT layer, typically with the assistance of a static in-plane magnetic field [2]. This enables a three terminal MTJ-based concept that isolates the read/write path (Fig. 1), significantly improving the device endurance and read stability. Moreover, due to SOT spin transfer geometry, incubation time is negligible which allows for reliable switching operation at sub-ns timescales [4,5]. Here, we report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. We demonstrate low power sub-ns switching and pathways for further optimization. Finally, excellent endurance and absence of electro-migration effect of ultrathin SOT layers are shown.Integration flow: We used a SOT dedicated mask set in the imec 300 mm fab. The main steps of the integration process are summarized in Fig. 2: a SOT-MTJ stack is deposited on smooth bottom electrodes (BE), which are fabricated using a tungsten (W) damascene process. The MTJ is top pinned and consist of SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized (PMA) stack, where the SOT layer is W-based. Specific stop etch conditions have been developed to leave the SOT layer intact while patterning the MTJ pillar without producing sidewall shorts across the MgO barrier (Fig. 2c,d). Subsequently, the SOT layer is etched to form the three terminal device and a dual damascene Cu top electrode (TE) was fabricated to complete the electrical connection ( Fig. 2a).Stack development: SOTs possess a damping-like term (τDL) attributed to spin Hall and a field-like term (τFL) attributed to interface interactions [2]. Recent work indicates that τDL triggers switching while τFL accelerates it [5]. Charge-to-spin conversion efficiency parameters θDL and...

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