Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Wu, Lizhou; Rao, Siddharth; Taouil, Mottaqiallah; Marinissen, Erik Jan; Kar, Gouri Sankar; Hamdioui, Said

doi:10.1109/itc50571.2021.00022

Cited by 5 publications

(1 citation statement)

References 190 publications

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“…3) Device-Aware Test Development for SAFF Defects: Based on the fault modeling results, we propose a magnetic march test, which is the first in the test community. It aims at guaranteeing the detection by incorporating magnetic write operations in the March test [28]:…”

Section: B Dat For Stt-mramsmentioning

confidence: 99%

Recent Trends and Perspectives on Defect-Oriented Testing

Bernardi

Cantoro

Coyette

et al. 2022

2022 IEEE 28th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cellaware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from 0PPM to 0PPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.

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Section: B Dat For Stt-mramsmentioning

confidence: 99%