Si:C alloys are potential candidates for source-drain stressor applications meant for n-type FinFETs. To function as an effective stressor, the substitutional C concentration (Csub) must be ≥ 1.5%. Increasing the C content to achieve high strain results in local arrangement of a fraction of Csub atoms in the form of third nearest neighbors (3 nn). We investigate if this 3 nn arrangement can be controlled by choosing optimal growth conditions and we also explore if this arrangement has an impact on the thermal stability of the Si:C layers, if they are subjected to high temperature processing. For a given Csub concentration, the use of a cyclic deposition and etching scheme reduces the 3 nn distribution in comparison to a single step deposition process. The 3 nn concentration also varied with respect to the choice of the Si precursor. Faster growth rates and adding in-situ doping did not significantly influence the 3 nn concentration for disilane, whereas the 3 nn concentration was considerably lower if trisilane was used as Si precursor. For the Si:C layers with comparable crystalline quality, the Csub loss during thermal annealing did not show a regular trend with respect to 3 nn distribution.