This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer from severe distortion of C-V due to tunneling current, resulting in poor oxide thickness extraction. The distortion can be suppressed using high frequencies in series model or using short gate lengths in parallel model. Considering instrument limits and manufacturability, however, the parallel model is more desirable. The distortion can be completely suppressed up to 10 4 A/cm 2 of tunneling current, using gate lengths shorter than 0.2 m in parallel model.
Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.
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